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Construction of The GPS Devices
Hort, Marek ; Jaroš, David (referee) ; Šteffan, Pavel (advisor)
Aim of this Diploma thesis was to create a device capable of receiving navigational data from GPS. These data are subsequently stored in fixed memory and after connection with the PC are displayed it on the satellite map. The device was realized by using FPGA and GPS module LEA-5s. Description was created in the VHDL language, which was implemented into the circuit. The part of VHDL design was description of PICOBLAZE processor that controls whole system. For displaying and archiving data stored in device was created PC application GPS TRACER. It is able to display stored trace on the satellite map by using Google maps server. For created device were designed and manufactured PCBs, which were manually fitted.
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Dynamic reconfiguration with Atmel FPSLIC
Jančík, Martin ; Hanák, Pavel (referee) ; Fedra, Zbyněk (advisor)
This study describes the platform Atmel FPSLIC, which is created by means of the logic arrays FPGA and the micro-sequencer controller AVR. The developmental kit STK594 is described here as well, with its programming possibilities, as for the logic arrays FPGA, as for the micro-sequencers AVR. Also the separate circuit AT94K is described there. This circuit can be programmed by the language VHDL (the field FPGA), or by means of the assembler and language C for the micro-sequencer. All this can be integrated into the one output file by means of program System Designer, comprising a set of software tools for given programming languages and for generation of the whole circuit. Furthermore, the study describes a simple application for the both platform parts. Also the description of the dynamic reconfiguration of the circuit gate part is included.
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OFDM demodulator implementation in FPGA
Solar, Pavel ; Urban, Josef (referee) ; Maršálek, Roman (advisor)
The master's thesis briefly analyses the principle of OFDM modulation, possibilities of the synchronization and channel estimation in OFDM. The simply model of OFDM system is made in MATLAB. Because of the implementation in FPGA is generated the behavioral description of the OFDM demodulator through the combination of the schematics description and the description in the VHDL language. The ISE development environment is used.
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Design of hardware cipher module
Bayer, Tomáš ; Stančík, Peter (referee) ; Sobotka, Jiří (advisor)
This diploma’s thesis discourses the cryptographic systems and ciphers, whose function, usage and practical implementation are analysed. In the first chapter basic cryptographic terms, symmetric and asymetric cryptographic algorithms and are mentioned. Also usage and reliability are analysed. Following chapters mention substitution, transposition, block and stream ciphers, which are elementary for most cryptographic algorithms. There are also mentioned the modes, which the ciphers work in. In the fourth chapter are described the principles of some chosen cryptographic algorithms. The objective is to make clear the essence of the algorithms’ behavior. When describing some more difficult algorithms the block scheme is added. At the end of each algorithm’s description the example of practical usage is written. The chapter no. five discusses the hardware implementation. Hardware and software implementation is compared from the practical point of view. Several design instruments are described and different hardware design programming languages with their progress, advantages and disadvantages are mentioned. Chapter six discourses the hardware implementation design of chosen ciphers. Concretely the design of stream cipher with pseudo-random sequence generator is designed in VHDL and also in Matlab. As the second design was chosen the block cipher GOST, which was designed in VHDL too. Both designs were tested and verified and then the results were summarized.
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USB communication protocol analysis
Zošiak, Dušan ; Fujcik, Lukáš (referee) ; Šteffan, Pavel (advisor)
Tato práce je zaměřena na zpracování a analýzu USB komunikačního protokolu a implementace jeho jednotlivých částí do FPGA obvodu s využitím programovacího jazyka VHDL. Ve finální podobě by měla práce představovat souhrnný a ucelený dokument popisující principy USB rozhraní a jeho komunikace doplněných praktickým návrhem v jazyce VHDL, který by byl schopen převést data do USB.
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Methods for quadrature modulator imbalance compensation
Povalač, Karel ; Valenta, Václav (referee) ; Maršálek, Roman (advisor)
Quadrature modulator (demodulator) is used in transmitting (receiving) part of many devices. Unwanted imbalance can influence amplitude, phase or DC offset of modulator (demodulator). Correction of imbalance was a main subject of thesis. Simulations of these methods were created in MATLAB and results were compared. Basics of methods were implement on programmable logic field by program Xilinx ISE. Development kit V2MB1000 with analogue board Memec P160 was chosen for this purpose. In the last part were compare simulation results with practical measurement.
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OFDM implementation in FPGA
Horák, Martin ; Fedra, Zbyněk (referee) ; Maršálek, Roman (advisor)
The thesis is focused on designing OFDM modem, which should be implemented into the FPGA device. The advantages of using OFDM signals in order to provide high baud rates together with high multipath immunity has provoked a mass expansion into media systems such as DSL, DVB, Wi-Fi, WLAN, etc. . Thanks to this technology we can quarantee high modulation rates with minimal negative disturbance eects. The rst part is dedicated to characterise OFDM signals, their generation and the algorithm producing the OFDM which is implemented in DSP devices. For the purpose of using the fastest algorithm, the Fast Fourier Transform using Cooley-Tukey algorithm was shown. Before we can implement OFDM modem into the FPGA device, we have to simulate its correct function. Because there is no OFDM analyser available at our departement, its necessary to prove its correct function by simulations. Therefore a large part of this thesis is focused on simulations using Matlab and ModelSim, in order to show comparison between the theoretical, and simulated results. Between the theoretical and practical simulations there is a part which shows the brief characteristics of available FPGA devices. Detailed view is presented just for the Virtex II device, which the implementation is made for. As a suitable FPGA device, we have chosen Virtex II XC2V1000 which is available for students. In the last part the measured results were shown to prove the corect function of the modem. Programming the FPGA using VHDL language is realized in the software ISE Xilinx (distributed in Xilinx software support). All programmed scrits and data used in this thesis are included on distributed media.
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Implementation of AES Algorithm on FPGA
Smékal, D.
This paper presents a VHDL (Very High Speed Integrated Circuit Hardware Description Language) implementation of 128-bit AES (Advanced Encryption Standard) on FPGA card (FieldProgrammable Gate Array) using Virtex-7 FPGA chip manufactured by Xilinx company. In this project our main concern is to implement all modules of this algorithm on hardware.
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Design Retiming na HDL úrovni
Kafka, Leoš ; Matoušek, Rudolf
This paper deals with an improvement of design timing characteristics by modification at the high abstraction level of the system description. Some synthesis tools such as Synplify Pro provide timing optimizations, called pipelining and retiming. These techniques help the designer unify delay slacks at different inputs, which results in higher system clock frequencies of the produced circuit.
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Dynamic runtime partial reconfiguration in FPGA
Matoušek, Rudolf ; Daněk, Martin ; Pohl, Zdeněk ; Kadlec, Jiří
Runtime dynamic reconfiguration of FPGA devices has been an issue of the last decade. Although this feature permits more robust and more flexible designes and devices that posseses it are available on the market, it is not directly supported by the current design tools. This paper presents a simple design that uses true dymnamic reconfiguration for Atmel AT94K devices. The design has been implemented using a special feature of the currently available Figaro IDS5.2 tool in an innovative way.
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