Original title: Dynamic runtime partial reconfiguration in FPGA
Authors: Matoušek, Rudolf ; Daněk, Martin ; Pohl, Zdeněk ; Kadlec, Jiří
Document type: Papers
Conference/Event: ECMS 2003 /6./, Liberec (CZ), 2003-06-02 / 2003-06-04
Year: 2003
Language: eng
Abstract: Runtime dynamic reconfiguration of FPGA devices has been an issue of the last decade. Although this feature permits more robust and more flexible designes and devices that posseses it are available on the market, it is not directly supported by the current design tools. This paper presents a simple design that uses true dymnamic reconfiguration for Atmel AT94K devices. The design has been implemented using a special feature of the currently available Figaro IDS5.2 tool in an innovative way.
Keywords: FPGA; runtine dynamic reconfiguration; VHDL
Project no.: CEZ:AV0Z1075907 (CEP), IST-2001-34016 (CEP)
Funding provider: EU IST
Host item entry: ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals

Institution: Institute of Information Theory and Automation AS ČR (web)
Document availability information: Fulltext is available at the institute of the Academy of Sciences.
Original record: http://hdl.handle.net/11104/0131206

Permalink: http://www.nusl.cz/ntk/nusl-34993


The record appears in these collections:
Research > Institutes ASCR > Institute of Information Theory and Automation
Conference materials > Papers