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Industrial HD camera interface
Juřica, Libor ; Dvořák, Vojtěch (referee) ; Bohrn, Marek (advisor)
Master´s thesis deals with creating circuit for receiving data from industrial camera. IP Core is designing for FPGA. Theoretical part of the work describes SDI interface, analysis of relevant SMPTE standards and specification of data format. The thesis include general characteristics of multigigabit transceivers. Practical part include VHDL description of SDI receiver. Thesis presents simulations of created circuit, implementation for real application and measurement results for signal transmission over slip ring.
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Implementation of fast serial bus on FPGA
Drbal, Jakub ; Dvořák, Vojtěch (referee) ; Pristach, Marián (advisor)
This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.
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Design and realization of acoustic camera
Koníček, Cyril ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
This thesis deals with design and realization of acoustic camera for sound source location. The essence of the device is microphone field listening for acoustic impulses which are processed in real-time in order to locate the source. Found location is displayed on LCD together with images from regular video camera. FPGA is used as a computational unit.
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Implementation of video compression into FPGA chip
Tomko, Jakub ; Fujcik, Lukáš (referee) ; Bohrn, Marek (advisor)
This thesis is focused on the compression algorithm's analysis of MJPEG format and its implementation in FPGA chip. Three additional video bitstream reduction methods have been evaluated for real-time low latency applications of MJPEG format. These methods are noise filtering, inter-frame encoding and lowering video's quality. Based on this analysis, a MJPEG codec has been designed for implementation into FPGA chip XC6SLX45, from Spartan-6 family.
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Graphics controller for FPGA
Rolko, Maroš ; Bohrn, Marek (referee) ; Pristach, Marián (advisor)
This diploma thesis is about design of a 2D graphics controller for FPGA circuits. It consists of two parts. In the first phase, it analyses 2D acceleration and interface for communication with display devices of the operation system Linux. The second part contains design of graphics controller itself and its implementation. Part of the thesis is description of components that the controller consists of and evaluation of resultant implementation. For testing purposes on selected FPGA circuit, test modules adding support for used peripherals and test data generation are created.
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Design of the user-friendly touch screen GUI and a physical connection to an existing simulation hardware device
Husar, Jan ; Kaczmarczyk, Václav (referee) ; Štohl, Radek (advisor)
Práce uvádí základní informace o průmyslové sběrnici AS-Interface a popisuje její funkce. Dále se zabývá rozšířením stávajícího FTZ AS-Interface Slave Simulátoru o dotykový display, který značně usnadní ovládání tohoto simulačního nástroje. Je zde nastíněn návrh a řešení uživatelského dotykového rozhraní k tomuto simulátoru s použitím Amulet LCD modulu STK 480272C. Vývoj tohoto rozhraní je proveden pomocí GEMstudia, softwaru firmy Amulet Technologies a grafických programů. Dále tato studie pojednává o softwarové úpravě FTZ AS-i Slave Smilulátoru. Jedná se o úpravu řídícího FPGA v jazyce VHDL zajišťující komunikaci s dotykovým displejem. Poslední kapitola se týká problematiky spojené s návrhem uživatelsky přívětivé aplikace.
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Signal and data logger
Borsányi, Tamás ; Vyskočil, Pavel (referee) ; Kolouch, Jaromír (advisor)
The goal of this project is to design a signal and data logger, which captures analog and digital signals with very long record time. The device supports multichannel complex triggering, a real-time oscilloscope-like mode and an offline mode for analyzing of previously sampled data. This project contains detailed analysis of the topic, description of hardware and software solutions and used methods. The thesis also contains verification tests and measurements. This device will be mainly used for hardware debugging of microprocessor based applications.
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Protection of highspeed communication systems
Smékal, David ; Martinásek, Zdeněk (referee) ; Hajný, Jan (advisor)
The diploma thesis deals with 128–bit AES data encryption and its implementation in FPGA network card using VHDL programming language. The theoretical part explains AES encryption and decryption, its individual steps and operating modes. Further was described the VHDL programming language, development environment Vivado, FPGA network card Combo–80G and configurable framework NetCOPE. The practical part is the implementation of AES–128 in VHDL. A simulation was used to eliminate errors, then the synthesis was performed. These steps were made using Vivado software. Last step of practical part was testing of synthesized firmware on COMBO–80G card. Total of 4 projects were implemented in FPGA card. Two of them were AES encryption and decryption with ECB mode and another two describe the encryption and decryption with CBC mode.
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Implementation of algorithm for energetic material measurement in FPGA device
Slovák, Jiří ; Moravec, Jaroslav (referee) ; Maršálek, Roman (advisor)
In the text of the master´s thesis, it is at first briefly referred about Energetic Material Measurement topic in general. Emphasis is placed especially at the description of the Velocity of Detonation and short analysis of selected measurement method. The most significant part of the paper is dedicated to the design and description of the system that was created in ISE Design Suite environment using VHDL language. The development was performed with respect to oncoming integration into the board with FPGA and A/D converters. The operation of detection algorithm which was created based on the MATLAB model was verified in the final part of the thesis by simulation of processing of real optical probe signals.
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