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Flexible Load Balancer Using P4 Language
Šesták, Jindřich ; Fukač, Tomáš (referee) ; Martínek, Tomáš (advisor)
Currently servers of internet services are usually grouped together into clusters to provide sufficient performance to serve clients' queries. Each cluster needs Load Balancer, so it can choose one server which will process query from one client. For describing such device that processes packets is convenient to use P4 language. Within this work, the principles of load balancing, design, implementation and testing of a simple Load Balancer described in P4 language were demonstrated. The program is tested using Behavioral model of P4 language on a common processor and on the NFB-200G2QL card thanks to the Netcope environment from the CESNET association
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Protection Against DoS Attacks Using P4 Language
Vojanec, Kamil ; Fukač, Tomáš (referee) ; Kučera, Jan (advisor)
This thesis focuses on reimplementation of existing DoS (Denial of Service) attack mitigation device with high-level P4 programming language. The main reason for using P4 is to enhance adaptability and functionality to different types of DoS attacks. The created device is designed in a modular way and enables easy alterations by using interchangeable components. The target platform for this thesis is an FPGA acceleration card. The work results in designing several DoS mitigation components and implementing applications composed of these components. Pats of this work have been presented at IEEE ANCS (Symposium on Architectures for Networking and Communication Systems) in September 2019 at University of Cambridge.
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Acceleration of Open vSwitch
Vodák, David ; Orsák, Michal (referee) ; Martínek, Tomáš (advisor)
Virtual switch is a program, which is used for connecting virtual machines to network and that is why it is a crucial part of server virtualization. However virtual switch is consuming too much performance of the server which it is running on. A measurement of Open vSwitch (OvS) indicates that for data speed of 10 Gb/s, approximately 4 cores of the processor are fully occupied. As the consumption of performance is directly proportional to transmission speed, it may eventually get to the point where the consumption of performance cannot be handled. This bachelor thesis is about acceleration of the Open vSwitch with the help of the DPDK Poll Mode Driver extended by support of the SR-IOV virtualization technology as well as the interface for offloading classification rules to hardware called RTE flow. In the scope of this thesis the SR-IOV is implemented and then tested on OvS. Furthermore, the RTE flow support was designed and partially implemented.
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High level synthesis in network applications described using P4 language
Panák, Petr ; Šťáva, Martin (referee) ; Fujcik, Lukáš (advisor)
High-level synthesis is a compelling method of designing a digital circuit. High abstraction and faster verification are advantages which aren't pressent in Register Transfer Level designing. That guarantees faster designing with lower development costs. This bachelor thesis deals with a digital design of actions, extern blocks and MI32 interface access. Each component design is described using C/C++ programming language and synthesised with Intel HLS compiler.
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P4 cryptographic primitive support
Cíbik, Peter ; Malina, Lukáš (referee) ; Smékal, David (advisor)
This diploma thesis deals with the problem of high-speed communication security which leads to the usage of hardware accelerators, in this case high-speed FPGA NICs. Work with simplification of development of FPGA hardware accelerator applications using the P4 to VHDL compiler. Describes extension of compiler of cryptographic external objects support. Teoretical introduction of the thesis explains basics of P4 language and used technologies. Describes mapping of external objects to P4 pipeline and therefore to FPGA chip. Subsequently deals with cryptographic external object, compatible wrapper implementation and verification of design. Last part describes implementation and compiler extension, cryptographic external object support and summarizes reached goals.
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P4 Language-Based Description of Accelerated Device against DoS Attacks
Kuka, Mário ; Kekely, Lukáš (referee) ; Kučera, Jan (advisor)
This thesis describes the development of a networking device used to defend against (D)DoS attacks using P4 language. The main purpose was to design flexible device using P4 lan-guage based on already existing device, this would allow us to quickly react and respond to new more complex DDoS attacks. The design of the device dealt with the transfer of individual parts of the firmware into the P4 language. Subsequently, the entire device firmware was designed for hardware accelerators with FPGA technology. The firmware had been designed with respect to the limitations of current P4 language compilers. The device has been tested under laboratory conditions for functionality and performance. The device will be deployed in the network infrastructure of CESNET.
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The Stateful Packet Processing in P4 Language
Kohout, Pavel ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
With the growing speed and complexity of computer networks, arise requirements for creating powerful devices that are capable of collecting statistics and changing their own functionality according to the demands of network administrators. These requirements can be described using specialized programming languages such as P4. In this bachelor thesis a design, implementation, testing and integration of register and counter stateful memory modules into P4 compiler system for FPGA technology was made. The created system supports the collection of statistics described in P4 language at speeds up to 100 Gbps.
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Remote Configuration of P4 Device
Neruda, Jakub ; Kučera, Jan (referee) ; Wrona, Jan (advisor)
Administration of a large network from a central node with a vendor independent API is quite important issue these days. The concept of SDN was truly helpful with realization of the solution, namely in the form of the OpenFlow protocol. Nowadays, a P4 language is gaining momentum, primarily thanks to its ability to describe whole packet processing pipeline and also for the P4 Runtime, solution to the distributed network configuration. CESNET association is one of the research groups starting to support P4 in their network cards beloging to the Combo series. In this work, an API was designed for these cards, aimed at the dynamic flow table configuration. This API was used for implementation of a basic support of the Combo cards in the P4 Runtime.
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OVS Acceleration Using FPGA Acceleration Card
Vido, Matej ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
The performance of the virtual switch Open vSwitch (OVS) is insufficient to satisfy the current requirements for link bandwidth of the server connections. There is an effort to accelerate the OVS both in the software and in the hardware by offloading the datapath to the smart network interface cards. In this work the COMBO card for 100G Ethernet developed by CESNET is used to accelerate the OVS. The suggested solution utilizes the firmware for FPGA generated from the definition in the P4 language to classify the packets in the card and DPDK for the data transfers and offloading the classification rules into the card. Forwarding of one flow with the shortest frames from physical to physical interface using one CPU core reaches forwarding rate of 11.2 Mp/s (10 times more than the standard OVS) with classification in the card and 5.9 Mp/s without classification in the card.
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System for Monitoring of Network Protocols
Selecký, Roman ; Dražil, Jan (referee) ; Kořenek, Jan (advisor)
It is necessary to monitor networks namely for diagnostics, troubleshooting, detection of anomalies and suspicious header encapsulations. This thesis aims to design and implement a system for monitoring protocol structure on 10 Gb networks, which will be able to capture packets based on the sequence of encapsulated protocols. To achieve requested throughput some tasks like packet parsing and packet filtering were accelerated in FPGA. Flexibility is achieved by using a tool that maps P4 programs, which define packet parsing process, to VHDL language. Based on the information gained from packet parsing, flow records are created and stored via IPFIX protocol. This information is displayed through a graphical user interface in the form of protocol tree, whose nodes are associated with flow records.
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