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Graphics display unit
Szkandera, Filip ; Dvořák, Vojtěch (referee) ; Dvorský, Adam (advisor)
The goal of this thesis is to learn about the function of a graphical unit and to design a simple version of it. The first chapter consists of a theory about a different connectors and protocols, that were typically used in graphical applications throughout history. Based on this theoretical analysis the best connector and a protocol for a graphical application is chosen. In the practical part of this thesis, the graphical unit is designed firstly using only logic integrated circuits and then using an FPGA.
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High-speed data transfer
Šimík, Jakub ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This work deals with the design of a device for sending data from a fast ADC converter to a computer via an Ethernet interface using the MicroZed 7020 development board and the Zynq 7000 system on chip that this board is equipped with. This development board and the Zynq 7000 are first presented in the work, followed by a brief description of the selected protocols, and based on a theoretical analysis, the design of the solution architecture is then carried out. The next part of the work then deals with the implementation of the device in programmable logic and software for the processing system according to the design architecture. The conclusion of the work is dedicated to verifying the correct function of individual parts of the device.
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The Quiet Omnipresence
Bodlák, Ondřej ; Dvořák, Vojtěch (referee) ; Mikyta, Svätopluk (advisor)
The work, entitled The Quiet Omnipresence, themes the metaphor of grid and line as representing the source elements necessary for the growth of whole forms. It relies on a study of landscape and urban scenery, its quiet ubiquitous mechanisms and processes. The jumble of lines creates a sensorially elusive monochromatic surface that the observer can encounter when looking at organic structures for longer periods, as well as industrially tuned urban compositions. It explores the relationship of order and chaos in its opposite but paradoxically mutually inexorable connotations. The work mostly relies on a specific and not uncommon type of space often right in the middle of cities – vague terrains, places forgotten and deliberately overlooked, in which banal biological processes slowly take the helm determining the direction of a seemingly random development.
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Design and simulation of branch predictor
Liberda, Dominik ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Predikce větvení hraje fundamentální roli ve výkonu procesorů. Predikce výsledku větví umožňuje procesoru spekulativně vykonávat instrukce dřív než je výsledek větve znám. Tato práce navrhuje vylepšený algoritmus pro predikci větvení a zároveň přepracovává simulační framework CBP2016 pro testování prediktorů větvení.
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High-speed packet accumulation in FPGA
Beneš, David ; Pristach, Marián (referee) ; Dvořák, Vojtěch (advisor)
Tato práce popisuje návrh číslicového obvodu, který má potenciál snížit režii přenosu malých paketů na komunikační lince mezi vysokorychlostní síťovou kartou s FPGA a hostitelským počítačem. Tento obvod je určen speciálně pro platformu NDK vyvinutou sdružením CESNET z.s.p.o., proto je první kapitola věnována její specifikaci. Motivace k sepsání této práce je popsána v následující kapitole, která je věnována komunikační lince mezi hostitelským počítačem a FPGA. Poslední část popisuje návrh číslicového obvodu a jeho testování jak z pohledu funkčnosti, tak z propustnosti.
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Verification environment for BLDC motor controller
Kalocsányi, Vít ; Kajan, Michal (referee) ; Dvořák, Vojtěch (advisor)
Tato práce se věnuje požadavku na důkladnou verifikaci při návrhu systému řízení BLDC motorů. V práci je vysvětlena funkční verifikace číslicových obvodů a univerzální verifikační metodika (UVM) a práce je zaměřena na návrh verifikačního prostředí s využitím této metodologie. Dále je v této práci vysvětlena typická struktura systému řízení BLDC motoru a definován způsob verifikace takového systému řízení. Dále je popsána implementace verifikačního prostředí a diskutovány přínosy zavedení UVM do verifikačního procesu.
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Picture generation using path tracing
Áč, Ondřej ; Dvořák, Vojtěch (referee) ; Pavlík, Michal (advisor)
This thesis deals with the problematics of computer-generated imagery using path tracing. The goal of this work is to create interactive computer program, which allows editing and rendering of photorealistic images of various scenes in real time. The work presents the concept of rendering equation, along with its known solutions, in the theoretical part of the work. Thesis describes in detail the solution using path tracing, based on the Monte Carlo integration technique, along with the benefits, it provides compared to the other techniques. Several hardware and software optimizations are then presented. Practical part of the work focuses on analysis of C++ source code and compiled assembly code whilst using hardware specific SIMD optimizations. Mandatory part of work is also the demonstration of program’s functionality, along with the measurements of achieved performance gains using manual optimizations.
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FFT implementation in FPGA and ASIC
Dvořák, Vojtěch ; Bohrn, Marek (referee) ; Fujcik, Lukáš (advisor)
The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation will be done in Matlab and then this form of implementation will be used as a reference model for implementation of fast Fourier transform algorithm in VHDL. To verify the correctness ofdesign verification enviroment will be created and verification process wil be done. Program that will generate source code for various parameters of the module performing a fast Fourier transform will be created in the last part of this thesis.
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High-Level Synthesis of Digital Circuits
Jendrušák, Ján ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.
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HLS development tool for DSP with custom programming language
Pastušek, Václav ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Nowadays, there are many different high-level syntheses for describing digital circuits. The best known ones generate VHDL code from programming languages such as ANSI C, C++, SystemC, SystemVerilog and MATLAB. But not everyone will identify with that type of programming, so sometimes it's good to go to a higher level of abstraction, where the internals of the components are hidden, and then the components are called with inputs and outputs. This thesis deals with the design of HLS, the design of input pseudocode, pseudo-libraries, compiler created in Python, its modules and practical application.
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