Original title: Low-latency AES encryption for High-Frequency Trading on FPGA
Authors: Cíbik, Peter ; Růžek, Michal ; Dvořák, Milan
Document type: Papers
Language: eng
Publisher: Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract: This paper presents a Field Programmable Gate Array (FPGA) powered low–latency solution for secure communication with the stock exchange. It presents architecture design and optimization techniques used to ensure the required security level without impacting the latency, which is the most critical domain in High-Frequency Trading (HFT). The National Stock Exchange of India (NSE) chose Advanced Encryption Standard (AES) with 256 bit key length in Galoise-Counter Mode (GCM) as the encryption algorithm for Non-NEAT Front End (NNF) connections.
Keywords: AES; Cryptography; Decryption; Encryption; Field–Programmable Gate Array; FPGA; GCM; Hardware acceleration; HFT; High- Frequency Trading; National Stock Exchange of India; NSE; VHDL
Host item entry: Proceedings I of the 30st Conference STUDENT EEICT 2024: General papers, ISBN 978-80-214-6231-1, ISSN 2788-1334

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: https://hdl.handle.net/11012/249242

Permalink: http://www.nusl.cz/ntk/nusl-622540


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