Original title: Instruction Mapping Process on the VLIW Architectures
Authors: Mego, Roman
Document type: Papers
Language: eng
Publisher: Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract: This paper deals with the process of instruction mapping on the digital signal processors. This process is used by the newly developed tool, which is designed for generating low-level assembly code for very long instruction word processors. The tool is suitable for creating cores of the signal processing algorithms.
Keywords: digital signal processing; instruction mapping; low-level; very long instruction word
Host item entry: Proceedings of the 22nd Conference STUDENT EEICT 2016, ISBN 978-80-214-5350-0

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/83961

Permalink: http://www.nusl.cz/ntk/nusl-613779


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Universities and colleges > Public universities > Brno University of Technology
Conference materials > Papers