Original title: Návrh testeru paměti RAM ve VHDL
Translated title: RAM-Tester Design in VHDL
Authors: Charvát, Jiří ; Straka, Martin (referee) ; Strnadel, Josef (advisor)
Document type: Master’s theses
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta informačních technologií
Abstract: [cze] [eng]

Keywords: address decoder.; DRAM; dynamic memory; error; march test; memory; memory cell; RAM; SRAM; static memory; Test; chyby; dekodér adres.; DRAM; dynamická paměť; March test; paměť; paměťová buňka; RAM; SRAM; statická paměť; Test; VHDL

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/53954

Permalink: http://www.nusl.cz/ntk/nusl-579966


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2024-04-02, last modified 2024-04-03


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