Original title: Komunikace uvnitř hardwarově akcelerovaného obvodu
Translated title: Communication in a hardware accelerated circuit
Authors: Rosa, Michal ; Jedlička, Petr (referee) ; Smékal, David (advisor)
Document type: Bachelor's theses
Year: 2023
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]

Keywords: AES; Cryptograhy; FPGA; IP block; Nexys A7-100T; VHDL; Xilinx; AES; FPGA; IP blok; Kryptografia; Nexys A7-100T; VHDL; Xilinx

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/214025

Permalink: http://www.nusl.cz/ntk/nusl-533515


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Bachelor's theses
 Record created 2023-09-10, last modified 2023-09-10


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