Original title: Universal asynchronous receiver/transmitter implementation in VHDL
Authors: Prášil, Pavel ; Petyovský, Petr
Document type: Papers
Language: eng
Publisher: Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract: The article deals with the design of an asynchronous serial receiver/transmitter and its implementation into the FPGA. The design will be used as a laboratory exercise in the course ”Logical circuits and systems”. This paper contains the basic design of UART and the following features which will be added. UART design will be used as a communication interface between PC and an existing programmable multichannel sound generator (PSG) design, which is already implemented in FPGA.
Keywords: FPGA; programmable multichannel sound generator; UART; VHDL
Host item entry: Proceedings I of the 28st Conference STUDENT EEICT 2022: General papers, ISBN 978-80-214-6029-4

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/209293

Permalink: http://www.nusl.cz/ntk/nusl-524720


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Conference materials > Papers