Original title: VHDL-based Implementation Of NTT On FPGA
Authors: Jedlička, Petr
Document type: Papers
Language: eng
Publisher: Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract: This paper is focused on the effective hardware-accelerated implementation of NTT (NumberTheoretic Transform) and inverse NTT (NTT-1) on FPGA (Field Programmable Gate Array).The discussed implementation is intended for the use in the lattice-based cryptography schemes, e.g.CRYSTALS-Dilithium digital signature scheme which is one of the finalists of the third round in thepost-quantum standardization process under the auspices of NIST (The National Institute of Standardsand Technology). The implementation of NTT (NTT-1) requires 1798 (2547) Look-Up Tables(LUTs), 2532 (3889) Flip-Flops (FFs) and 48 (84) Digital Signal Processing blocks (DSPs). The latencyof the design is 502 (517) clock cycles at the frequency 637 MHz on Xilinx Virtex UltraScale+architecture which makes the presented implementation to be currently the fastest one. Regarding theinverse NTT, this is the first implementation at all.
Keywords: Dilithium; FPGA; Montgomery reduction; NTT; VHDL
Host item entry: Proceedings II of the 27st Conference STUDENT EEICT 2021: Selected papers, ISBN 978-80-214-5943-4

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/200828

Permalink: http://www.nusl.cz/ntk/nusl-447872


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