Original title: Implementace PCS podvrstvy 400 Gb/s Ethernetu v FPGA
Translated title: Implementation of 400 Gb/s Ethernet PCS layer to FPGA
Authors: Kolařík, Jaroslav ; Pristach, Marián (referee) ; Fujcik, Lukáš (advisor)
Document type: Master’s theses
Year: 2019
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]

Keywords: 400GBASE-R; Ethernet; FPGA; PCS; VHDL; 400GBASE-R; Ethernet; FPGA; PCS; VHDL

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/177772

Permalink: http://www.nusl.cz/ntk/nusl-399472


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2019-08-26, last modified 2022-09-04


No fulltext
  • Export as DC, NUŠL, RIS
  • Share