Original title: An FPGA-based fault injector for TSC circuits
Translated title: Injektor poruch pro TSC obvody založený na FPGA
Authors: Kafka, Leoš
Document type: Papers
Conference/Event: Počítačové architektury a diagnostika 2005. PAD 2005, Lázně Sedmihorky (CZ), 2005-09-21 / 2005-09-23
Year: 2005
Language: eng
Abstract: [eng] [cze]
Newer FPGA devices are more susceptible to faults, especially transient faults. Some kind of concurrent error detection approach has to be used to avoid system failure due to these aults. To obtain the totally self checking property is the goal in most cases, but it's often impossible. It's useful to evaluate numbers of detectable and undetectable faults. An FPGA-based fault injector capable to get these values is presented in this paper. It's implemented in Atmel FPSLIC and uses dynamic reconfiguration. Článek se zabývá simulací poruch v úplně samočinně kontrolovaných obvodech implementovaných v FPGA. Pro simulaci poruch byl použit softwarový simulátor a hardwarový injektor, využívající dynamickou rekonfiguraci pro vkládání poruch. Článek obsahuje výsledky experimentů a porovnání obou metod.
Keywords: concurrent error detection; fault simulation; FPGA
Project no.: CEZ:AV0Z10750506 (CEP), 1QS108040510 (CEP)
Funding provider: GA MŠk
Host item entry: Počítačové architektury a diagnostika

Institution: Institute of Information Theory and Automation AS ČR (web)
Document availability information: Fulltext is available at the institute of the Academy of Sciences.
Original record: http://hdl.handle.net/11104/0131514

Permalink: http://www.nusl.cz/ntk/nusl-35090


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Research > Institutes ASCR > Institute of Information Theory and Automation
Conference materials > Papers