Original title: Implementace koncového bodu v síti SpaceWire do FPGA
Translated title: SpaceWire Endpoint implementation
Authors: Hráček, Marek ; Fujcik, Lukáš (referee) ; Dvořák, Vojtěch (advisor)
Document type: Bachelor's theses
Year: 2016
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]

Keywords: communication network; endpoint; FPGA; interface; SpaceWire; VHDL; FPGA; komunikační síť; koncový bod; rozhraní; SpaceWire; VHDL

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/61536

Permalink: http://www.nusl.cz/ntk/nusl-255075


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Bachelor's theses
 Record created 2016-09-20, last modified 2022-09-04


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