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Srovnání rychlosti akustického signálu s mechanickými vlastnostmi dřeva javoru
Fišer, Petr
Práce byla zpracována na základě porovnání šíření rychlosti akustického signálu ve dřevě javoru a habru. Dalším úkolem v této práci bylo zjistit závislosti šíření rychlosti akustického signálu v porovnání s mechanickými vlastnostmi ve dřevě javoru. Měření rychlosti akustického signálu bylo měřeno akustickým tomografem Fakopp ArborSonic 3D a mechanické vlastnosti byly měřeny v univerzálním testovacím stroji ZWICK Z 050. Použity byly vzorky z jednoho javoru a jednoho habru, které rostly v urbanizovaném prostředí.
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Mapping of packet processing from P4 Language to FPGA Technology
Kekely, Michal ; Fišer, Petr (oponent) ; Zilberman, Noa (oponent) ; Kořenek, Jan (vedoucí práce)
This thesis deals with the design of novel hardware architectures for packet classification. The main goal is to propose general and flexible hardware approaches capable of classifying packets on high-speed computer networks. The approaches need to be configurable via P4 language description and need to be scaleable to 100 Gbps and faster networks. The thesis starts with an analysis of the current state of the art in packet classification on high-speed networks. Based on the analysis, new architectures for packet classification are proposed. The architectures are designed with scalability, flexibility, and memory efficiency in mind. The goal is to achieve high throughput while maintaining P4-programmability and the ability to carry out general packet classification. Proposed approaches are further optimized and extended to be as efficient as possible. The first architecture uses the DCFL algorithm extended by a parallel TCAM memory, memory duplication and ruleset analysis. The goal is to achieve general packet classification, which has small memory requirements and offer a trade-off between the achieved throughput and the memory requirements. The second proposed approach is more specialized. It optimizes exact match packet classification by leveraging the distributed memories on FPGAs to speed up the Cuckoo hashing algorithm. The main goal is to achieve very high throughputs efficiently. Both approaches are further extended by proposing a caching mechanism that enables efficient external memory usage. Finally, all of the proposed mechanisms are evaluated on real network data, and the achieved results are shown.
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Evolutionary Synthesis of Complex Digital Circuits
Kocnová, Jitka ; Fišer, Petr (oponent) ; Trefzer,, Martin (oponent) ; Vašíček, Zdeněk (vedoucí práce)
The research presented in this thesis focuses on the field of evolutionary optimization of complex combinational circuits. The work begins with a study of the existing conventional and nonconventional approaches to the optimization of combinational circuits. Features and issues connected with the internal circuit representations commonly used by present synthesis tools. Boolean networks and their scalability were discussed. Attention was also paid to the evolutionary synthesis, with focus on the CGP (Cartesian Genetic Programming). A new approach to the evolutionary optimization of combinational circuits was proposed. By extracting a sub-circuit containing a suitable number of gates of the original circuit and by optimizing this sub-circuit by the CGP, it was possible to reduce the number of gates of the circuit significantly more than by optimizing the whole circuit by the CGP. For the extraction phase, three methods were proposed. The first method is based on the cut computing algorithm. This method was able to reduce the number of gates of every benchmark circuit and it overcame the results of the globally working CGP in majority of cases. The second method is based on the windowing algorithm. This allows to expand the sub-circuit selection with the gates in the output direction of the root node of the selection and not only with the gates in its input direction. This method significantly improved the results obtained by using the cut-based method. It also overcame the issue of the cut-based method with selecting the sub-circuit near the primary inputs of the circuit and thus creating a selection too small for a subsequent optimization. The third method is based on the reconvergent-paths selection algorithm. The existence of a reconvergent-path in the sub-circuit increases the probability of presence of don't care nodes and thus the higher efficiency of the optimization. Also, an evolutionary optimization method targeting the non-uniform delay on the sub-circuit's inputs. By using this method, it is possible to extract and optimize a sub-circuit without an influence on the delay of the whole circuit. By applying the principle of local evolutionary optimization, a significantly better gate reduction of the circuits was achieved then by applying the CGP optimization on whole cir- cuits. However, it is important to choose the sub-circuit's root node carefuly with respect to its position in the circuit. Also, it is necessary to set the parameters of evolution, extraction and the whole optimization process carefully (e.g. the number of gates in each sub-circuit, number of CGP generations and number of sub-circuits that should be optimized).
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Use of verification for testing fault-tolerance in FPGA-based system
Podivínský, Jakub ; Fišer, Petr (oponent) ; Racek, Stanislav (oponent) ; Kotásek, Zdeněk (vedoucí práce)
Fault tolerance is one of the most commonly used techniques to eliminate the effect of faults on digital systems and increase their reliability. This work presents a platform for testing such fault tolerance techniques targeted to FPGA-based systems. The platform uses the principles of functional verification, while the experimental electronic controller is moved to the FPGA, which allows the use of fault injection directly into the FPGA. The platform makes it possible to use the electro-mechanical application as an experimental system and allows to monitor the effect of faults on both the electronic controller and the behavior of controlled mechanical part. This work presents experiments with two experimental systems - robot for finding a path through a maze and an electronic lock. The platform is designed to allow the use of any experimental system with an electronic control unit implemented in the FPGA
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Analytický řešič pro pevnostní výpočet náprav dvojkolí
Fišer, Petr ; Náhlík, Luboš (oponent) ; Vaverka, Michal (vedoucí práce)
Tato diplomová práce se zabývá nápravami dvojkolí kolejových vozidel, jejich návrhem a způsobu provádění pevnostních analýz jejich konstrukčních řešení. V rámci této práce byl proveden návrh lokomotivního dvojkolí: nápravy a kola. Pro potřeby konstrukčního oddělení společnosti Bonatrans Group a.s. byl vytvořen analytický řešič, který umožňuje provádění pevnostních analýz pomocí, kterým je výsledný návrh verifikován a navíc umožňuje vytištění pevnostní analýzy v podobě výpočtové zprávy, jež slouží schvalování příslušnými drážními úřady. V takto vytvořeném analytickém řešiči byla následně vytvořena i pevnostní analýzu takto navržené nápravy.
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Automated Multi-Objective Parallel Evolutionary Circuit Design and Approximation
Hrbáček, Radek ; Fišer, Petr (oponent) ; Trefzer,, Martin (oponent) ; Sekanina, Lukáš (vedoucí práce)
Recently, energy efficiency has become one of the most important properties of computing platforms, especially because of limited power supply capacity of battery-power devices and very high consumption of growing data centers and cloud infrastructure. At the same time, in an increasing number of applications users are able to tolerate inaccurate or incorrect computations to a certain extent due to the imperfections of human senses, statistical nature of data processing, noisy input data etc. Approximate computing, an emerging paradigm in computer engineering, takes advantage of relaxed functionality requirements to make computer systems more efficient in terms of energy consumption, computing performance or complexity. Error resilient applications can achieve significant savings while still serving their purpose with the same or a slightly degraded quality. Even though new design methods for approximate computing are emerging, there is a lack of methods for automated approximate HW/SW design offering a rich set of compromise solutions. Conventional methods often produce solutions that are far from an optimum. Evolutionary algorithms have been shown to bring innovative solutions to complex design and optimization problems. However, these methods suffer from several problems, such as the scalability or a high number of fitness evaluations needed to evolve competitive results. Finally, existing methods are usually single-objective whilst multi-objective approach is more suitable in the case of approximate computing. In this thesis, a new automated multi-objective parallel evolutionary algorithm for circuit design and approximation is proposed. The method is based on Cartesian Genetic Programming. In order to improve the scalability of the algorithm, a brand new highly parallel implementation was proposed. The principles of the NSGA-II algorithm were used to provide the multi-objective design and approximation capability. The performance of the implementation was evaluated in multiple different applications, in particular (approximate) combinational arithmetic circuits design, bent Boolean functions discovery and approximate logic circuits for TMR schema. In these cases, important improvements with respect to the state of the art were obtained.
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Přehled nových trendů v konstrukci krátkých palných zbraní.
Fišer, Petr ; Hort, Filip (oponent) ; Svoboda, Petr (vedoucí práce)
Cílem bakalářské práce je vytvoření přehledu konstrukčních provedení krátkých palných zbraní a to pistolí a revolverů. První kapitola bakalářské práce obsahuje rozbor hlavních a ostatních částí, ze kterých jsou pistole a revolvery složeny. V následující kapitole je historický vývoj s rozdělením dle základních konstrukčních provedení a s popisem několika provedení pistolí a revolverů. Poslední kapitola hodnotí současný a budoucí trend vývoje v konstrukcích krátkých palných zbraní.
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Automated Design Methodology for Approximate Low Power Circuits
Mrázek, Vojtěch ; Bosio, Alberto (oponent) ; Fišer, Petr (oponent) ; Sekanina, Lukáš (vedoucí práce)
The rapid expansion of modern embedded and battery-powered systems has brought new challenges for design methods oriented to low power circuits and systems. Although these methods systematically apply various power optimization techniques, the overall power requirements are still growing because of the increased complexity of integrated circuits. It has been shown that many applications are inherently error resilient and this property can be exploited for further power consumption reduction. This principle is systematically investigated in the nascent field of approximate computing. This thesis deals with efficient design methods for approximate circuits. The proposed methods are based on evolutionary algorithms (EAs). Although EAs have been applied in logic synthesis and optimization of common as well as approximate circuits, their scalability is limited in these areas. The goal of this dissertation is to show that approximate logic synthesis based on evolutionary algorithms (particularly on genetic programming) can provide excellent tradeoffs between the error and power consumption of complex digital circuits. We analyzed four different applications that use digital circuits described at three different levels of abstraction. By means of Cartesian genetic programming we reduced power consumption of small transistor-level circuits that are typically used in a technology library. We combined evolutionary approximation with formal verification techniques in order to evolve high quality gate-level approximate circuits such as adders and multipliers and provide formal guarantees on the approximation error. These circuits were employed to reduce power consumption in neural image classifiers and discrete cosine transform blocks of the HEVC encoder. We proposed a new data-independent error metric - the distance error - and used it in the evolutionary approximation of complex median circuits that are suitable for low power signal processing. This doctoral thesis presents a coherent methodology for the design of approximate circuits at different levels of description which is also capable of providing formal guarantees on the approximation error.
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Výsuvná zadní náprava malého městského automobilu
Fišer, Petr ; Veselý, Oldřich (oponent) ; Koutný, Daniel (vedoucí práce)
Diplomová práce se zabývá návrhem a konstrukcí netradičního nosného rámu zadní nápravy malého městského užitkového automobilu. Rám umožňuje změnu rozvoru náprav pomocí vysouvání zadní části. Automobil tak může být dle potřeby používán v krátké nebo dlouhé užitkové verzi. Hlavní část práce popisuje návrh variant řešení, výběr varianty a popis hlavních částí zvoleného konstrukčního řešení. Práce je uzavřena popisem výroby výsuvné zadní nápravy.
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