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Mapping of packet processing from P4 Language to FPGA Technology
Kekely, Michal ; Fišer, Petr (oponent) ; Zilberman, Noa (oponent) ; Kořenek, Jan (vedoucí práce)
This thesis deals with the design of novel hardware architectures for packet classification. The main goal is to propose general and flexible hardware approaches capable of classifying packets on high-speed computer networks. The approaches need to be configurable via P4 language description and need to be scaleable to 100 Gbps and faster networks. The thesis starts with an analysis of the current state of the art in packet classification on high-speed networks. Based on the analysis, new architectures for packet classification are proposed. The architectures are designed with scalability, flexibility, and memory efficiency in mind. The goal is to achieve high throughput while maintaining P4-programmability and the ability to carry out general packet classification. Proposed approaches are further optimized and extended to be as efficient as possible. The first architecture uses the DCFL algorithm extended by a parallel TCAM memory, memory duplication and ruleset analysis. The goal is to achieve general packet classification, which has small memory requirements and offer a trade-off between the achieved throughput and the memory requirements. The second proposed approach is more specialized. It optimizes exact match packet classification by leveraging the distributed memories on FPGAs to speed up the Cuckoo hashing algorithm. The main goal is to achieve very high throughputs efficiently. Both approaches are further extended by proposing a caching mechanism that enables efficient external memory usage. Finally, all of the proposed mechanisms are evaluated on real network data, and the achieved results are shown.
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Evolutionary Synthesis of Complex Digital Circuits
Kocnová, Jitka ; Fišer, Petr (oponent) ; Trefzer,, Martin (oponent) ; Vašíček, Zdeněk (vedoucí práce)
The research presented in this thesis focuses on the field of evolutionary optimization of complex combinational circuits. The work begins with a study of the existing conventional and nonconventional approaches to the optimization of combinational circuits. Features and issues connected with the internal circuit representations commonly used by present synthesis tools. Boolean networks and their scalability were discussed. Attention was also paid to the evolutionary synthesis, with focus on the CGP (Cartesian Genetic Programming). A new approach to the evolutionary optimization of combinational circuits was proposed. By extracting a sub-circuit containing a suitable number of gates of the original circuit and by optimizing this sub-circuit by the CGP, it was possible to reduce the number of gates of the circuit significantly more than by optimizing the whole circuit by the CGP. For the extraction phase, three methods were proposed. The first method is based on the cut computing algorithm. This method was able to reduce the number of gates of every benchmark circuit and it overcame the results of the globally working CGP in majority of cases. The second method is based on the windowing algorithm. This allows to expand the sub-circuit selection with the gates in the output direction of the root node of the selection and not only with the gates in its input direction. This method significantly improved the results obtained by using the cut-based method. It also overcame the issue of the cut-based method with selecting the sub-circuit near the primary inputs of the circuit and thus creating a selection too small for a subsequent optimization. The third method is based on the reconvergent-paths selection algorithm. The existence of a reconvergent-path in the sub-circuit increases the probability of presence of don't care nodes and thus the higher efficiency of the optimization. Also, an evolutionary optimization method targeting the non-uniform delay on the sub-circuit's inputs. By using this method, it is possible to extract and optimize a sub-circuit without an influence on the delay of the whole circuit. By applying the principle of local evolutionary optimization, a significantly better gate reduction of the circuits was achieved then by applying the CGP optimization on whole cir- cuits. However, it is important to choose the sub-circuit's root node carefuly with respect to its position in the circuit. Also, it is necessary to set the parameters of evolution, extraction and the whole optimization process carefully (e.g. the number of gates in each sub-circuit, number of CGP generations and number of sub-circuits that should be optimized).
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Řízení výkonnosti procesů v podnicích DZP
Marcineková, Katarína
Důvodem zabývání se optimalizací interních procesů ve firmě je zvýšení celkové výkonnosti výroby a tím i její konkurenceschopnosti. V současnosti se podíl nábytkářského průmyslu na celkovém HDP Slovenské republiky zvyšuje, avšak stále představuje jen jeho velmi malou část. Navíc vzhledem k přírodnímu bohatství země je důležité, abychom se věnovali optimalizaci odvětví, která patří do dřevozpracujícího průmyslu. Disertační práce se zabývá problematikou použití numerických metod matematické optimalizace výroby nábytku, díky kterým lze řešit i lineární nepopsatelné procesy, jejichž cíle mají protichůdný charakter. Při optimalizaci je důležité zaměřit se na klíčový a kritický subproces za účelem maximalizace produktivity, kvality a minimalizace nákladovosti prostřednictvím identifikace vstupních parametrů a výstupních cílových veličin. Pod pojmem klíčový subproces rozumíme ten, který se v největší míře podílí na celkové efektivnosti výrobního procesu. Z hlediska jeho identifikace je důležité determinovat podíl jednotlivých produktů na celkovém objemu výroby případně podíl jejich krycích příspěvků. Kritický subproces představuje prostor pro zlepšení a lze jej identifikovat na základě určení zmetků v jednotlivých aktivitách a rovněž je třeba respektovat technologický postup, z čehož vyplývá, že chyby v prvních fázích výrobního procesu mají vyšší vliv na jeho celkovou výkonnost. Na základě analýzy ve sledovaném nábytkářském podniku byla identifikována kritická činnost- frézování. Optimální hodnoty vstupních parametrů vzhledem k cílovým veličinám byly determinovány prostřednictvím použití umělých neuronových sítí (UNS), přičemž v experimentu byly použity dva druhy nástrojových materiálů – diamant (PKD) a slinutý karbid (T03SMG). Nakonec byl vytvořen komplexní model subprocesů výroby nábytku, který představuje principiální postup optimalizace a návrh modulárního řešení informačního systému pro podniky DZP v odvětví nábytkářské výroby.
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Lattice-based Threshold Signature Optimization for RAM Constrained Devices
Shapoval, Vladyslav ; Ricci, Sara
The DS2 scheme is a lattice-based (n, n)-threshold signature based on the standardized Dilithium signature. However, deploying DS2, as well as Dilithium, on microcontrollers is a challenge due to the memory limitations of these devices. While the decryption phase can be implemented relatively straightforwardly, the key generation and signing phases require the generation and manipulation of large matrices and vectors, which can quickly exhaust the available memory on the microcontroller. In this paper, we propose an optimization of the DS2 key generation and signing algorithms tailored for microcontrollers. Our approach focuses on minimizing memory consumption by generating large elements, such as the commitment key ck and the random commitment parameter r, on the fly from random and non-random seeds. This approach significantly reduces the overall size of the signature from 143 KB to less than 5 KB, depending on the number of signers involved. We also split the algorithms into two distinct components: a security-critical part and a non-security-critical part. The security-critical part contains operations that require secret knowledge and must be run on the microcontroller itself. Conversely, the non-critical part contains operations that do not require secret knowledge and can be performed on a connected, more powerful central host.
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Mapping and analyzing of signal coverage of 4G/5G mobile networks
Baránek, Michal ; Polák, Ladislav ; Kufa, Jan
This paper addresses the enhanced measurement of signal coverage, capacity, and reliability in mobile networks, particularly with the growing prevalence of 4G and 5G technologies. Given the escalating importance of these networks in everyday activities, there arises a demand for open-source solutions to evaluate and enhance their performance effectively. The objective of this research is to analyze gathered data to pinpoint areas necessitating network enhancements and to develop opensource software and hardware solutions for extracting essential performance metrics (KPIs) from 4G/5G networks. The proposed system offers an interface for assessing network performance and signal coverage, enabling cost-efficient measurements across diverse environments.
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Application of Optimization Algorithms to Support Penetration Testing
Žáček, Dominik ; Lazarov, Willi
This paper presents a novel approach to support the pre-engagement phase of penetration testing, where testing tasks are assigned to penetration testers based on their knowledge and experience to ensure the most appropriate selection. To apply and verify our approach, we developed an automated tool that uses optimization algorithms for the task assignment process. Experimental testing shows that the application of algorithms based on optimization problems in the first phase of penetration testing could be a way to increase its effectiveness.
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Automatic production line efficiency evaluation and optimization
Štěrba, Zdeněk ; Kaczmarczyk, Václav
The article deals with the analysis of the production line in terms of overall efficiency. The aim is to define the areas that play a role in overall efficiency and then devise appropriate solutions to improve them. Emphasis is placed on the analytical method Basic MOST designed for work norming, according to which the normalized time of operators is determined. The next part of the paper is devoted to the analysis in order to find the weak points of the line that could be optimized in order to increase efficiency or financial savings. The production line and its analysis is also processed as a discrete event system in Siemens Plant Simulation software, focusing on the data flow and variability of the whole system.
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Příprava amidů 3,4-benzotropolon-karboxylové kyseliny
Panýrková, Gabriela ; Machara, Aleš (vedoucí práce) ; Rýček, Lukáš (oponent)
Tropolonové a benzotropolonové skelety, jež jsou součástí struktur řady přírodních látek, jsou spojovány s velkým množstvím velmi zajímavých biologických účinků. Tato bakalářská práce se zabývá přípravou derivátů 3,4,6-trihydroxy-5H-benzo[7]annulen-5-onu, tedy dehydroxypurpurogallinu včetně dalších možných příprav jeho derivátů za využití enzymatické katalýzy a jejich následným dalším využitím. Hlavní důraz je ovšem kladen na přípravu kyseliny 3,4-benzotropolon-karboxylové a přípravu množství jejích amidů spolu s optimalizací amidační reakce. Dále byly prozkoumány palladium katalyzované karboxylace na enzymaticky připraveném bromderivátu dehydroxypurpurogallinu. Klíčová slova tropolony, benzotropolony, dehydroxypurpurogallin-4-karboxylová kyseliny, amidy, optimalizace, enzymatická katalýza, karboxylace
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Optimalizace systému Suricata zredukovaním mezivláknových závislostí
Kríž, Adam ; Setinský, Jiří (oponent) ; Šišmiš, Lukáš (vedoucí práce)
In the age of the internet, connection to the global network is possible from almost any type of device. Just to name a few: a fridge, a front door, a smart watches and more. With the growing number of devices that require an internet connection, the security and protection of the user's privacy comes to the foreground. One of the solutions that can be ensured network protection is Suricata, which is used to detect network threats and events. It can deploy as a monitoring system or it can be an active prevention system. Aim of this work will be optimizing the Suricata system in IDS mode (Intrusion Detection System ). As a result of the work, certain data structures will be changed, which will reduce cross-thread dependencies. The result will be an expected increase in performance in the form of savings processor time and increasing the volume of processed packets at the same time. Achieved results will be described in detail and evaluated at the end of the bachelor's thesis.
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