Original title: Implementace vrstvy RS-FEC pro 400 Gb/s Ethernet
Translated title: RS-FEC layer implementation for 400Gb/s ethernet
Authors: Zahálka, Patrik ; Kekely, Lukáš (referee) ; Vyroubal, Petr (advisor)
Document type: Master’s theses
Year: 2020
Language: eng
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [eng] [cze]

Keywords: 400 Gb/s Ethernet; FPGA; Reed-Solomonovy samoopravné kódy; 400 Gbps Ethernet; Forward Error Correction; FPGA; Reed-Solomon Error Correction Codes

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/189374

Permalink: http://www.nusl.cz/ntk/nusl-413233


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2020-07-11, last modified 2022-09-04


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