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Graphical User Interface for Packet Generator
Chromčák, Michal ; Kováčik, Michal (referee) ; Matoušek, Jiří (advisor)
According to increasing requirements on speed of different software and hardware components, there are solutions, which can, by principle, reach better parameters, then solutions commonly known. One of them is to use software with hardware acceleration on the field of generating synthetic network traffic. Exactly this way a packet generator was implemented, in current version without graphical user interface. But to let this system spread into the target group of users, there is need to implement also this interface. This bachelor's thesis describes proposal of graphical interface, its implementation in JavaFX programming language, testing on real users and tutorial demonstrating how to use this interface.
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Network Traffic Simulation and Generation
Matoušek, Jiří ; Kořenek, Jan (referee) ; Korček, Pavol (advisor)
Development of computer networks able to operate at the speed of 10 Gb/s imposes new requirements on newly developed network devices and also on a process of their testing. Such devices are tested by replaying synthetic or previously captured network traffic on an input link of the tested device. We must be able to perform both tasks also at full wire speed. Current testing devices are either not able to operate at the speed of 10 Gb/s or they are too expensive. Therefore, the aim of this thesis is to design and implement a hardware accelerated application able to generate and replay network traffic at the speed of 10 Gb/s. The application is accelerated in the FPGA of the COMBOv2 card and it also utilizes the NetCOPE platform. Architecture of the application is modular, which allows easy implementation of different modes of operation. The application implements both capturing and replaying network traffic at full wire speed, but traffic can be limited to a specified value of bitrate at the output. The thesis is concluded by a comparison of the implemented application and the packet generator implemented on the NetFPGA platform. According to this comparison, the implemented application is better than the NetFPGA packet generator.
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Verification of Intrusion Detection System
Košař, Vlastimil ; Martínek, Tomáš (referee) ; Tobola, Jiří (advisor)
This thesis focuses on verification of Intrusion Detection System and its IPv6 support extension. Here are described posibilities of SystemVerilog for verification, choosen verification methodology, pros and cons of different verification and testing approaches. Here is designed structure of verification of key parts of Intrusion Detection System. The key component of verification system is Packet Generator.
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Network Traffic Simulation and Generation
Matoušek, Jiří ; Kořenek, Jan (referee) ; Korček, Pavol (advisor)
Development of computer networks able to operate at the speed of 10 Gb/s imposes new requirements on newly developed network devices and also on a process of their testing. Such devices are tested by replaying synthetic or previously captured network traffic on an input link of the tested device. We must be able to perform both tasks also at full wire speed. Current testing devices are either not able to operate at the speed of 10 Gb/s or they are too expensive. Therefore, the aim of this thesis is to design and implement a hardware accelerated application able to generate and replay network traffic at the speed of 10 Gb/s. The application is accelerated in the FPGA of the COMBOv2 card and it also utilizes the NetCOPE platform. Architecture of the application is modular, which allows easy implementation of different modes of operation. The application implements both capturing and replaying network traffic at full wire speed, but traffic can be limited to a specified value of bitrate at the output. The thesis is concluded by a comparison of the implemented application and the packet generator implemented on the NetFPGA platform. According to this comparison, the implemented application is better than the NetFPGA packet generator.
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Flood attacks generation
Hudec, David
Proposal of a high speed packet flooding device is presented in this paper. The product is based on the FPGA (Field-programmable Gate Array) platform, developed in VHDL (Very high speed integrated circuit Hardware Description Language) and set into the NetCOPE environment. It uses an existing solution of packet generator. Once done, it should be implemented on a COMBO-80G board to serve as a network stressing tool.
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Verification of Intrusion Detection System
Košař, Vlastimil ; Martínek, Tomáš (referee) ; Tobola, Jiří (advisor)
This thesis focuses on verification of Intrusion Detection System and its IPv6 support extension. Here are described posibilities of SystemVerilog for verification, choosen verification methodology, pros and cons of different verification and testing approaches. Here is designed structure of verification of key parts of Intrusion Detection System. The key component of verification system is Packet Generator.
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Graphical User Interface for Packet Generator
Chromčák, Michal ; Kováčik, Michal (referee) ; Matoušek, Jiří (advisor)
According to increasing requirements on speed of different software and hardware components, there are solutions, which can, by principle, reach better parameters, then solutions commonly known. One of them is to use software with hardware acceleration on the field of generating synthetic network traffic. Exactly this way a packet generator was implemented, in current version without graphical user interface. But to let this system spread into the target group of users, there is need to implement also this interface. This bachelor's thesis describes proposal of graphical interface, its implementation in JavaFX programming language, testing on real users and tutorial demonstrating how to use this interface.
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