Original title: Flood attacks generation
Authors: Hudec, David
Document type: Papers
Language: eng
Publisher: Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract: Proposal of a high speed packet flooding device is presented in this paper. The product is based on the FPGA (Field-programmable Gate Array) platform, developed in VHDL (Very high speed integrated circuit Hardware Description Language) and set into the NetCOPE environment. It uses an existing solution of packet generator. Once done, it should be implemented on a COMBO-80G board to serve as a network stressing tool.
Keywords: Denial of Service; DoS; FPGA; NetCOPE; network attack; network tester; packet generator; VHDL
Host item entry: Proceedings of the 22nd Conference STUDENT EEICT 2016, ISBN 978-80-214-5350-0

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/83862

Permalink: http://www.nusl.cz/ntk/nusl-383580


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Universities and colleges > Public universities > Brno University of Technology
Conference materials > Papers