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Hardware Acceleration of Header Field Extraction
Polčák, Libor ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
Most network devices need to obtain specific packet header fields belonging to different network protocol headers for correct functionality. This work aims to create an efficient unit capable of application-specific packet header analysis and data extraction. The proposed unit deals with protocols used on L2, L3, and L4 layers of ISO/OSI model including tunneled protocols; it is possible to specify protocols which are to be supported. Data analysis is based on right linear grammar transformed to finite automaton. Hardware acceleration has to be exploited in order to achieve data processing of all traffic exchanged over high-speed networks. Using FPGA technology it is possible to achieve both fast and configurable data processing. The designed unit is able to process data on up to 40 Gbps networks. On-the-fly configuration of extracted header fields is supported.
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Packet Parsing and Header Field Extraction in FPGA
Selecký, Roman ; Košař, Vlastimil (referee) ; Kořenek, Jan (advisor)
Network devices need to process packets and gather information from header fields. Packet parsers become outdated due to increasing number of protocols and frequent changes in their definitions. This thesis aims to create design of flexible and powerful packet parser. P4 language was designed to define packet processing. Flexible parsers can be constructed by combining potential of P4 with reconfigurable FPGA technology. Program mapping P4 language to designed architecture was implemented in order to promptly reflect changes in parser model.
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Hardware Acceleration of Analysis and Header Field Extraction
Polčák, Libor ; Tobola, Jiří (referee) ; Kořenek, Jan (advisor)
This work deals with packet analysis and processing for high speed networks using FPGA. Model of the analysis and hardware architecture have been proposed. Protocols can be specified in XML. Automated tool is able to convert this specification to VHDL. As mul- tiple bytes and protocol headers are processed within one clock cycle simultaneously, the proposed unit is able to handle packet processing on 10 Gbps speed and higher.
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Packet Parsing and Header Field Extraction in FPGA
Selecký, Roman ; Košař, Vlastimil (referee) ; Kořenek, Jan (advisor)
Network devices need to process packets and gather information from header fields. Packet parsers become outdated due to increasing number of protocols and frequent changes in their definitions. This thesis aims to create design of flexible and powerful packet parser. P4 language was designed to define packet processing. Flexible parsers can be constructed by combining potential of P4 with reconfigurable FPGA technology. Program mapping P4 language to designed architecture was implemented in order to promptly reflect changes in parser model.
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Hardware Acceleration of Analysis and Header Field Extraction
Polčák, Libor ; Tobola, Jiří (referee) ; Kořenek, Jan (advisor)
This work deals with packet analysis and processing for high speed networks using FPGA. Model of the analysis and hardware architecture have been proposed. Protocols can be specified in XML. Automated tool is able to convert this specification to VHDL. As mul- tiple bytes and protocol headers are processed within one clock cycle simultaneously, the proposed unit is able to handle packet processing on 10 Gbps speed and higher.
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Hardware Acceleration of Header Field Extraction
Polčák, Libor ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
Most network devices need to obtain specific packet header fields belonging to different network protocol headers for correct functionality. This work aims to create an efficient unit capable of application-specific packet header analysis and data extraction. The proposed unit deals with protocols used on L2, L3, and L4 layers of ISO/OSI model including tunneled protocols; it is possible to specify protocols which are to be supported. Data analysis is based on right linear grammar transformed to finite automaton. Hardware acceleration has to be exploited in order to achieve data processing of all traffic exchanged over high-speed networks. Using FPGA technology it is possible to achieve both fast and configurable data processing. The designed unit is able to process data on up to 40 Gbps networks. On-the-fly configuration of extracted header fields is supported.
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Hardware Packet Preprocessing for Acceleration of Network Applications
Vondruška, Lukáš ; Mikušek, Petr (referee) ; Tobola, Jiří (advisor)
This thesis particularly deals with design and implementation of FPGA unit, which performs hardware acclerated header field extraction of network packets. By utilizing NetCOPE platform it is proposed flexible and effective high-peformance solution for high-speed networks. A theoretical part presents a classical protocol model and an analysis of the Internet traffic. Main part of the thesis is further focused on key issues in hardware packet preprocessing, such as packet classification and deep packet inspection. The author of this thesis also discusses possible technology platforms, which can be utilized to acceleration of network applications.
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