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A Bit-Vector Compiler for Data-Flow Graphs
Sušovský, Tomáš ; Lengál, Ondřej (referee) ; Smrčka, Aleš (advisor)
The principal goal of this bachelor thesis is to design and implement a tool for compiling data-flow graph models to SMT-LIB format. This thesis builds on the research project HADES developed by VeriFIT research group of the Faculty of Information Technology, Brno University of Technology. The solution uses compiler for generating object model from original graph. Object model can be converted to a SMT-LIB format description including assertions of the desired system properties. Loop unrolling method (with user defined boundary for unrollment) is used for verification of system properties depending on changes in state of model. Capabilities of the developed tool are demonstrated on set of data-flow graphs models. Models cover usage of all elements defined in VAM language (input format) and their combinations. Result of this thesis presents new ways of processing data-flow graphs in VAM format and their verification.
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An Interactive Simulator for Data-flow Graphs
Kovařík, David ; Smrčka, Aleš (referee) ; Charvát, Lukáš (advisor)
Data-flow graphs are often used by hardware designers. Such graph representation is also very useful for performing deeper analysis of a design (including functional or formal verification). Simulator presented in this thesis is a support tool for verification environment HADES. The goal of the simulator is to decrease necessary time and increase quality of the verification process. To perform a simulation efficiently, a specific simulation algorithm which saves computation time by eliminating redundant evaluations has been introduced. The simulator is equiped with several output interfaces connected to a single simulation core. One output interface provides direct simulation output in text format. The second is also textual, but allows user to control the simulation. Finally, the third forms a graphical interface that visualizes simulation results.
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A Bit-Vector Compiler for Data-Flow Graphs
Sušovský, Tomáš ; Lengál, Ondřej (referee) ; Smrčka, Aleš (advisor)
The principal goal of this bachelor thesis is to design and implement a tool for compiling data-flow graph models to SMT-LIB format. This thesis builds on the research project HADES developed by VeriFIT research group of the Faculty of Information Technology, Brno University of Technology. The solution uses compiler for generating object model from original graph. Object model can be converted to a SMT-LIB format description including assertions of the desired system properties. Loop unrolling method (with user defined boundary for unrollment) is used for verification of system properties depending on changes in state of model. Capabilities of the developed tool are demonstrated on set of data-flow graphs models. Models cover usage of all elements defined in VAM language (input format) and their combinations. Result of this thesis presents new ways of processing data-flow graphs in VAM format and their verification.
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An Interactive Simulator for Data-flow Graphs
Kovařík, David ; Smrčka, Aleš (referee) ; Charvát, Lukáš (advisor)
Data-flow graphs are often used by hardware designers. Such graph representation is also very useful for performing deeper analysis of a design (including functional or formal verification). Simulator presented in this thesis is a support tool for verification environment HADES. The goal of the simulator is to decrease necessary time and increase quality of the verification process. To perform a simulation efficiently, a specific simulation algorithm which saves computation time by eliminating redundant evaluations has been introduced. The simulator is equiped with several output interfaces connected to a single simulation core. One output interface provides direct simulation output in text format. The second is also textual, but allows user to control the simulation. Finally, the third forms a graphical interface that visualizes simulation results.
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