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National Repository of Grey Literature 2 records found  Search took 0.00 seconds. 
Hardware Modelling in UGE
 Varga, Ladislav ; Očenášek, Pavel (referee) ; Smrčka, Aleš (advisor)
The goal of this thesis is to create a plugin for application Universal graphic editor, which will allow users to design a hardware architecture. Design of hardware architecture usualy starts with drawing of block diagrams of system which is being developed. Next step is to transcribe this drawn design into some hardware description language (HDL). Since structure of hardware design written in HDL is modular, i.e. similar to the structure of its block diagram, it's possible to translate block diagram of hardware design into HDL source code. The point of this idea is to get rid of designer's work on re-writing the block diagram into HDL language, as this can be automated. Designed plugin allows users to create block diagrams and new hardware components on different layers and switch between these layers interactively. Modul also implements the translation of drawn diagram into VHDL source code.
Detailed record
Hardware Modelling in UGE
 Varga, Ladislav ; Očenášek, Pavel (referee) ; Smrčka, Aleš (advisor)
The goal of this thesis is to create a plugin for application Universal graphic editor, which will allow users to design a hardware architecture. Design of hardware architecture usualy starts with drawing of block diagrams of system which is being developed. Next step is to transcribe this drawn design into some hardware description language (HDL). Since structure of hardware design written in HDL is modular, i.e. similar to the structure of its block diagram, it's possible to translate block diagram of hardware design into HDL source code. The point of this idea is to get rid of designer's work on re-writing the block diagram into HDL language, as this can be automated. Designed plugin allows users to create block diagrams and new hardware components on different layers and switch between these layers interactively. Modul also implements the translation of drawn diagram into VHDL source code.
Detailed record

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