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Methodology of highly reliable systems design
Straka, Martin ; Gramatová, Elena (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Methodology of Inserting Checkers into Digital System
Bartl, Michal ; Straka, Martin (referee) ; Kotásek, Zdeněk (advisor)
The topics described in this diploma thesis belong to the area of digital systems testability analysis. Basic concepts as dependability, controllability, observability and testability are explained. Methods of raising testability and dependability of digital circuits are mentioned including the metrics which allow to evaluate testability parameters. Furthermore, the thesis describes the formal model of digital systems which introduces the implementing part of the thesis. Within this part, a program tool is demonstrated, which allows to identify the components of digital circuits and their function. The other function of the program tool is to create control circuits that check the correct function of such digital circuits.
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Static Analysis of CodAL Language Source Code
Fajčík, Martin ; Přikryl, Zdeněk (referee) ; Hynek, Jiří (advisor)
The goal of bachelor's thesis is to design and implement extensions devoted to source code static analysis and automatic corrections used in CodAL language editors. This form of analysis is convenient e.g. for the source code semantic checks. The thesis consists of theoretical and practical part. Role of the theoretical part is to overview with extension development related to Eclipse platform, especially with the CodAL language editor, CodAL language itself and to define problems of this language which are suitable to be solved on the static analysis level. Practical part includes specific implementation details of the particular static analysis elements and automatic corrections. These extended CodAL language editors are available in integrated development environment Codasip Studio based first and foremost on the Eclipse platform and project CDT. Codasip Studio has been developed by company Codasip Ltd. in collaboration with Lissom research team.
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Polymorphic Self-Checking Circuits
Mazuch, Martin ; Růžička, Richard (referee) ; Sekanina, Lukáš (advisor)
This Master's thesis deals with question of the development of self-checking polymorphic circuits. It deals with a traditional way of creating reliable and self-checking circuits, presenting basic principles and methods. Also a method of Cartesian Genetic Programming for development of combinational circuits is explained. This thesis describes concepts of polymorphic gates and circuits and their benefits in practical use. Some existing self-checking polymorphic circuits are presented and their self-checking capabilities are analyzed. A proposal of realization of a design system for self-checking polymorphic circuits is given. A design system has been built based on presented specification and an application allowing simulations and analysis of system-proposed solutions has been created. Variety of experiments have been performed at created system and several interesting solutions have been acquired. At the end, conclusion is given and benefits of MSc. project are discussed.
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Static Analysis of CodAL Language Source Code
Fajčík, Martin ; Přikryl, Zdeněk (referee) ; Hynek, Jiří (advisor)
The goal of bachelor's thesis is to design and implement extensions devoted to source code static analysis and automatic corrections used in CodAL language editors. This form of analysis is convenient e.g. for the source code semantic checks. The thesis consists of theoretical and practical part. Role of the theoretical part is to overview with extension development related to Eclipse platform, especially with the CodAL language editor, CodAL language itself and to define problems of this language which are suitable to be solved on the static analysis level. Practical part includes specific implementation details of the particular static analysis elements and automatic corrections. These extended CodAL language editors are available in integrated development environment Codasip Studio based first and foremost on the Eclipse platform and project CDT. Codasip Studio has been developed by company Codasip Ltd. in collaboration with Lissom research team.
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Methodology of highly reliable systems design
Straka, Martin ; Gramatová, Elena (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Methodology of highly reliable systems design
Straka, Martin ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
|
|
|
Methodology of Inserting Checkers into Digital System
Bartl, Michal ; Straka, Martin (referee) ; Kotásek, Zdeněk (advisor)
The topics described in this diploma thesis belong to the area of digital systems testability analysis. Basic concepts as dependability, controllability, observability and testability are explained. Methods of raising testability and dependability of digital circuits are mentioned including the metrics which allow to evaluate testability parameters. Furthermore, the thesis describes the formal model of digital systems which introduces the implementing part of the thesis. Within this part, a program tool is demonstrated, which allows to identify the components of digital circuits and their function. The other function of the program tool is to create control circuits that check the correct function of such digital circuits.
|
|
|
Polymorphic Self-Checking Circuits
Mazuch, Martin ; Růžička, Richard (referee) ; Sekanina, Lukáš (advisor)
This Master's thesis deals with question of the development of self-checking polymorphic circuits. It deals with a traditional way of creating reliable and self-checking circuits, presenting basic principles and methods. Also a method of Cartesian Genetic Programming for development of combinational circuits is explained. This thesis describes concepts of polymorphic gates and circuits and their benefits in practical use. Some existing self-checking polymorphic circuits are presented and their self-checking capabilities are analyzed. A proposal of realization of a design system for self-checking polymorphic circuits is given. A design system has been built based on presented specification and an application allowing simulations and analysis of system-proposed solutions has been created. Variety of experiments have been performed at created system and several interesting solutions have been acquired. At the end, conclusion is given and benefits of MSc. project are discussed.
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Using the camera sensor in the measuring technique
Srba, Tomáš ; Čejka, Miloslav (referee) ; Bejček, Ludvík (advisor)
This bachelor thesis describes using of the Checkers in measuring technology, for control and picture comparing with picture reference by pixel match. Is describe part of machine vision as branch of industry automation. The bachelor thesis content summarized and described the basic methods, for image processing, function CCD and CMOS sensors, there are introduced standards of color signal encoding. Project this bachelor thesis is parameter checking of the checker. Special part of this work is description of working station for demonstration parameters checking of the checker. Program documentation of the Checker 101/E101 from COGNEX helps with design step by step.
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