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Lossless Data Compression for IP Networks
Pánek, Richard ; Kajan, Michal (referee) ; Korček, Pavol (advisor)
This bachelor's thesis deals with data compression methods in IP networks. The LZW compression algorithm and its history is described more in detail. This algorithm is tested on the di erent types of IP tracffic. It is shown that depending on the traffic type it is possible to reduce data to 70% of its original size. As the final implementation of the LZW algorithm is intented for use in the FPGA the results from high level synthesis (from C to VHDL language) are fi nally described.
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HDR Tone-Mapping Acceleration on Xilinx Zynq Platform
Nosko, Svetozár ; Zemčík, Pavel (referee) ; Musil, Martin (advisor)
This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.
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Acceleration of HTTTP Traffic Analysis
Budiský, Jakub ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This bachelor thesis addresses hardware accelerated analysis of HTTP, the most used protocol on the Internet. The goal is to extract substantial information from the HTTP headers and to achieve throughput needed for monitoring high-speed networks. The C language is used to create a software implementation which is then optimized for parallel environment and transformed into a hardware architecture using High Level Synthesis. Both solutions, software and hardware one, are tested on real traffic samples and their throughput is measured. Achieved results are discussed and new solution is proposed on their basis.
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HDR Tone-Mapping Acceleration on Xilinx Zynq Platform
Nosko, Svetozár ; Zemčík, Pavel (referee) ; Musil, Martin (advisor)
This diploma thesis focuses on the High-level synthesis (HLS). The first part deals with theoretical details and methods that are used in HLS tools. This is followed by a description of the synthesis tool Vivado HLS which will be used for implementation of an application. In the second part is briefly introduced high dynamic range images (HDR) and tone mapping. The third part is dedicated to design and implementation of the aplication which implements tone mapping methods in HDR images. This methods are implemented in Vivado HLS and language C++. This application is based on platform Xilinx Zynq and it uses multiexposure camera for capturing HDR images. Images are transmitted to FPGA for tone mapping processing.
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|
|
Acceleration of HTTTP Traffic Analysis
Budiský, Jakub ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This bachelor thesis addresses hardware accelerated analysis of HTTP, the most used protocol on the Internet. The goal is to extract substantial information from the HTTP headers and to achieve throughput needed for monitoring high-speed networks. The C language is used to create a software implementation which is then optimized for parallel environment and transformed into a hardware architecture using High Level Synthesis. Both solutions, software and hardware one, are tested on real traffic samples and their throughput is measured. Achieved results are discussed and new solution is proposed on their basis.
|
|
|
Lossless Data Compression for IP Networks
Pánek, Richard ; Kajan, Michal (referee) ; Korček, Pavol (advisor)
This bachelor's thesis deals with data compression methods in IP networks. The LZW compression algorithm and its history is described more in detail. This algorithm is tested on the di erent types of IP tracffic. It is shown that depending on the traffic type it is possible to reduce data to 70% of its original size. As the final implementation of the LZW algorithm is intented for use in the FPGA the results from high level synthesis (from C to VHDL language) are fi nally described.
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