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Testing of Probes for Network Traffic Monitoring
Sobol, Jan ; Korček, Pavol (referee) ; Kořenek, Jan (advisor)
In order to ensure a secure and stable Internet, administrators need tools for network monitoring which will allow them to analyze ongoing network traffic and respond to situations in a timely manner. One way to monitor traffic is to use monitoring probes. This thesis focuses on a thorough verification of the parameters of existing probes IPFIX probe and FlexProbe. FlexProbe is a network probe designed for the implementation of lawful interceptions developed at FIT BUT in cooperation with the Police of the Czech Republic. The IPFIX probe is developed by the CESNET association and is used for flow monitoring within the FlexProbe probe. In order to be able to operate the probes in the target environment for a long time, it is necessary to thoroughly test the device. The exact behavior of the probe is defined by the specification requirements that are developed for both probes. Based on the requirements, a comprehensive test system covering functional and performance parameters of the probes was designed. The tests are unified using a test framework and included in automated scenarios implemented in system Jenkins. At the end of the thesis, the coverage of the required properties of the probes and their performance is evaluated.
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Statefull Processing of TCP/IP Flows
Olbert, Jakub ; Žádník, Martin (referee) ; Kořenek, Jan (advisor)
The fast development of computer networks brings the necessity to protect those networks against more and more advanced attacks. The security systems require an advanced analysis for their operation which is carried out based on the stateful processing of flows. This Bachelor Thesis focuses on the proposal and simulation of the stateful flow processing system. The proposed system uses a specialized hardware for network operation processing acceleration of high-speed backbone lines. The specific feature of the system is the flow memory distribution between the hardware and software. The created simulation model will make it possible to test and optimize the stateful flow processing system already in the phase of proposal and thus the possible implementation will be facilitated.
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Hardware Acceleration of Algorithms for Approximate String Matching
Nosek, Ondřej ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
Methods for aproximate string matching of various sequences used in bioinformatics are crucial part of development in this branch. Tasks are of very large time complexity and therefore we want create a hardware platform for acceleration of these computations. Goal of this work is to design a generalized architecture based on FPGA technology, which can work with various types of sequences. Designed acceleration card will use especially dynamic algorithms like Needleman-Wunsch and Smith-Waterman.
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Hardware Acceleration of Analysis and Header Field Extraction
Polčák, Libor ; Tobola, Jiří (referee) ; Kořenek, Jan (advisor)
This work deals with packet analysis and processing for high speed networks using FPGA. Model of the analysis and hardware architecture have been proposed. Protocols can be specified in XML. Automated tool is able to convert this specification to VHDL. As mul- tiple bytes and protocol headers are processed within one clock cycle simultaneously, the proposed unit is able to handle packet processing on 10 Gbps speed and higher.
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Mutual Notification of Smart Phone and Server
Douděra, Martin ; Korček, Pavol (referee) ; Kořenek, Jan (advisor)
This thesis deals with notification between smart phone and application server which controls intelligent home. It is focused on Android mobile platform and it is implemented for that platform. Notification service Google Cloud Messaging is used because it is not possible to directly address mobile phones from server. Based on actual position and user defined area the server is informed about moving to or from the area. The server can perform defined event automatically with these information. Implementation was tested in real system. Alpha and beta versions were regularly published.
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EEG Biofeedback Human Brain - Computer Interface
Kněžík, Jan ; Kořenek, Jan (referee) ; Marušinec, Jaromír (advisor)
This master thesis dwells on EEGbiofeedback (also called Neurofeedback) interface of human brain and the computer and its concrete realization in Java programming language. This system is founded on the basis of the computer, which is accomplishing biological feedback (biofeedback) and the electroencephalography (EEG) by helping that state's scanning of user's brain is realized. By this way is possible to practise the human brain effectively to achieve better concentration, the elimination of sleeping and learning deficiency. Hereafter is the suggestion of direction control of computer mouse by EEG device incorporated, which makes it possible for the man to regulate the direction of the cursor's movement on the screen by the frequency of brain's oscillation. The motivation for solution of this problem is the effort to help to handicapped people to communicate with surrounding world. The introduction of this paper contains the basic facts about human brain, electroencephalography and EEG biofeedback. The following chapters dwell on the specification of claims to developed application, its suggestion and description of actual realization. The final part relates to the BCI (Brain-Computer Interface) systems and suggestion of computer's control by EEGappliance with evaluation of attained results.
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Network Flow Classification Using Look-Up Processor
Blaho, Juraj ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This work is about the design and the implementation of the software that is intended to configure the look-up processor used for an IPv4 and IPv6 packet classification. This work describes the algorithms used for the transformation of a user defined ruleset into the hardware configuration. The main goal is to set up the hardware acclerated filter called NIFIC which is based on a personal computer and the powerful acceleration card COMBO6. Performed tests show that it is possible to filter multi-gigabit network flows by using this developed software.
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Mapping of Algorithms to FPGA Using High-Level Synthesis Tools
Kupka, David ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This thesis deals with ways to describe hardware. It presents the methods used in the synthesis of the description and then it compares on a set of algorithms currently common low level description in VHDL with the newly emerging high-level synthesis, where a component is described at a algorithmic level in higher programming language. The object of comparison is the ratio of time required for implementation and optimality of the resulting components.
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Software Testing
Vadkerti, Miroslav ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
The aim of the thesis is to design a methodology for automatized source code testing for the project Liberouter. The designed methodology allows testing the compatibility and usability of the given software on a large scale of variants of supported platforms. The methodology is implemented in programming language Perl as an automatized server working with VMware Server virtualization software.
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Acceleration of Methods for Searching Palindroms and Repetitive Structures
Voženílek, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
Genetic information of all living organisms is stored in DNA. Exploring of its structure and function represents an important area of research in modern biology. One of the interesting structures occurring in DNA are palindromes. Based on the research they are expected to play an important role in interpreting the information stored in DNA, because they are often observed near important genes. Palindromes searching is complicated by the presence of mutations (changes in sequences of DNA elements), which increases the time complexity of algorithms. Therefore it is reasonable to study their parallelization and acceleration. The objective of this work is a study of palindromes searching methods and acceleration architecture design. The hardware unit implemented in a chip with FPGA technology placed on ml555 board can speed up the calculation up to 6 667 times in comparison with the best-known software method relying on suffix arrays.
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