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Metody návrhu a verifikace pro rekonfigurovatelné návrhy v obvodu Atmel FPSLIC
Kadlec, Jiří ; Daněk, Martin
This paper describes a methodology and design flow for designs with dynamic reconfiguration in the DSP and control domain. The described design flow starts with a description an Matlab/Simulink that is converted to Handel-C and then compiled through VHDL to EDIF, and finally to FPGA configuration. The methodology and design flow are demonstrated on implementation examples with simple floating-point IP cores targetting the Atmel AT94K FPSLIC device.
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Design Retiming na HDL úrovni
Kafka, Leoš ; Matoušek, Rudolf
This paper deals with an improvement of design timing characteristics by modification at the high abstraction level of the system description. Some synthesis tools such as Synplify Pro provide timing optimizations, called pipelining and retiming. These techniques help the designer unify delay slacks at different inputs, which results in higher system clock frequencies of the produced circuit.
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Dynamic reconfiguration of FPGAs: a case study
Matoušek, Rudolf
This paper discusses dynamic reconfiguration achievable using current FPGA methodology. An analysis of implementation issues has been presented and desirable features of future generation of CAD tools have been discussed. Several practical examples have been presented together with their implementation data.
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Dynamic reconfiguration of FPGAs
Matoušek, Rudolf ; Pohl, Zdeněk ; Daněk, Martin ; Kadlec, Jiří
Dymnamic reconfiguration of FPGA devices has been an issue of the last decade. Althouth this new feature of currently available devices permits more robust and flexible designs, it has not been recognized by professionals. This paper disscussed demands placed by dynamic reconfiguration on design tools as well as on designes themselves. A case study is presented for the Atmel AT94K family and the supplied design tools, and values are provided that should aid in analyzing such designs.
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Dynamic runtime partial reconfiguration in FPGA
Matoušek, Rudolf ; Daněk, Martin ; Pohl, Zdeněk ; Kadlec, Jiří
Runtime dynamic reconfiguration of FPGA devices has been an issue of the last decade. Although this feature permits more robust and more flexible designes and devices that posseses it are available on the market, it is not directly supported by the current design tools. This paper presents a simple design that uses true dymnamic reconfiguration for Atmel AT94K devices. The design has been implemented using a special feature of the currently available Figaro IDS5.2 tool in an innovative way.
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Podpora dynamické rekonfigurace pro AVR
Honzík, Petr
This paper presents a software core for an universal econfiguration system-on-a-programmable chip platform based on Atmel AT94K FPSLIC with an external FLASH memory. The AVR core controls basic functions that together with the FPSLIC platform creates a transparent infrastructure for software-driven FPGA reconfiguration.
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