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Acceleration of Algorithms for Approximate String Matching
Voženílek, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
The objective of this bachelor's thesis is to design and implement architecture for FPGA chips that accelerates matching of two strings and scoring them for similarity. Used processes come from bioinformatics algorithms, especially Needleman-Wunsch and Smith-Waterman. Due to general design and generic implementation in VHDL the unit is able to compare any sequences of characters, which is a task widely used in many branches of informatics from database searches (where approximate matching allows discovery of spelling errors) to spam detection. Depending on task specification the acceleration speed up against common software solution can reach orders of hundreds or even thousands.
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Automatic Grouping of Regular Expressions
Stanek, Timotej ; Kořenek, Jan (referee) ; Kaštil, Jan (advisor)
This project is about security of computer networks using Intrusion Detection Systems. IDS contain rules for detection expressed with regular expressions, which are for detection represented by finite-state automata. The complexity of this detection with non-deterministic and deterministic finite-state automata is explained. This complexity can be reduced with help of regular expressions grouping. Grouping algorithm and approaches for speedup and improvement are introduced. One of the approches is Genetic algorithm, which can work real-time. Finally Random search algorithm for grouping of regular expressions is presented. Experiment results with these approches are shown and compared between each other.
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Hardware Accelerating of Encryption Algorithm
Hradil, David ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
The goal of this thesis is to design a hardware realization of circuit which will implement the AES algorithm. A motivation was to make an acceleration against the classic software encryption. The acceleration is achieved by special designed parts of the circuit, which correspond to particular operations of the AES algorithm. First, there was necessary to design the circuit. In the next step there was a need to describe the designed circuit by the VHDL language. Then the circuit was simulated and synthesized. Due to comparing the circuit with software processing a software implementation was created. Both implementations were created for the FITKit platform. The hardware implementation is made by the FPGA technology and the software implementation is realized in a microcontroller. The result of the thesis is almost one thousandfold acceleration against the classic software encryption.
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Detection of Network Anomalies Based on NetFlow Data
Czudek, Marek ; Bartoš, Václav (referee) ; Kořenek, Jan (advisor)
This thesis describes the use of NetFlow data in the systems for detection of disruptions or anomalies in computer network traffic. Various methods for network data collection are described, focusing especially on the NetFlow protocol. Further, various methods for anomaly detection in network traffic are discussed and evaluated, and their advantages as well as disadvantages are listed. Based on this analysis one method is chosen. Further, test data set is analyzed using the method. Algorithm for real-time network traffic anomaly detection is designed based on the analysis outcomes. This method was chosen mainly because it enables detection of anomalies even in an unlabelled network traffic. The last part of the thesis describes implementation of the algorithm, as well as experiments performed using the resulting application on real NetFlow data.
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Implementation of Encryption Algorithms in VHDL Language
Kožený, Petr ; Martínek, Tomáš (referee) ; Kořenek, Jan (advisor)
This thesis deals with design and implementation of AES and DES encryption architectures for embedded systems. Architectures are implemented in VHDL language and design for FPGA technology. The proposed implementations are mapped on the Xilinx Spartan 3 technology. Both architectures are applied in simple ECB (Electronic Codebook) scheme with cache memories. A maximum throughput of design DES architecture 370 Mbps is achived with clock frequency of 104 MHz. The throughput of AES architecture at the maximum clock frequency of 118 MHz is 228 Mbps. Compared to software implementations for embedded systems, we achieve significantly higher throughput for both architectures.
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System of Internal Buses for Chips with FPGA Technology
Málek, Tomáš ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This thesis deals with design and implementation of interconnection bus system for chips with FPGA technology. The system ensures both communication between internal components on a chip and their communication with other computer elements which are mapped to the host system memory. The buses are high-speed, full duplex and packet-oriented and their architecture is based on tree topology. The data width is configurable, individually for every bus part. Due to this feature, it is possible to build uniform hierarchical system of internal buses with different speed that interconnects differently fast components. Proposed interconnection system was implemented in VHDL language and it is utilized in the Liberouter project which is the part of CESNET research intention Programable Hardware.
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Driver and Hardware Module of MiWi Protocol for Linux
Hala, Martin ; Kořenek, Jan (referee) ; Novotný, Tomáš (advisor)
The master's thesis is about a communication element - a hardware module, its design and implementation. The communication is to be maintained between a Linux embedded device and the sensors elements, using the MiWi protocol. The task is part of the IoT project, developed at FIT BUT. Furthermore, the paper describes design of a driver for the module, its likely solution, as well as the very implementation. Finally, the obtained experience is discussed in a summary, along the next step options on how to proceed further with the driver development.
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Time Synchronization in Computer Networks
Matoušek, Denis ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
The master's thesis deals with design of a solution for time synchronization in computer networks that is a crucial problem of many network applications. Based on analysis of protocols for time synchronization, PTP protocol was chosen as an appropriate candidate. The thesis describes the implementation of the design for a special network interface card and demonstrates features of the solution in several tests. A part of the solution processing precise timestamps was implemented in FPGA chip on the network card while PTP messages are processed in a software application. Values of configurable parameters of the application were determined based on analysis of the network card properties and results of particular tests. It was achieved accuracy in order of tens of nanoseconds.
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Library for Fast Network Traffic Processing
Vokráčko, Lukáš ; Viktorin, Jan (referee) ; Kořenek, Jan (advisor)
This thesis is focused on time-critical operations in context of computer networks. Processed operations are packet classification, specially one-dimensional classification, longest prefix matching using binary search on prefix length and TreeBitmap, pattern matching using Aho-Corasick, regular expression matching and packet header analysis and extraction. Purpose of this work is to design API for library implementing these operations. Implementation speed of these operations is measured on Intel and ARM platforms.
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Data Profiling Using IPFIX Mediator
Kozubík, Michal ; Bartoš, Václav (referee) ; Kořenek, Jan (advisor)
This thesis deals with the network data profiling using IPFIX mediator. The main task is effective data filtering and configurable profiles management. The profiles management is still not available for IPFIX mediator, which makes analysis of network traffic for users more difficult. Therefore this thesis deals with the design and implementation of configurable profiles management as a plug-in for IPFIX mediator. The plug-in uses profiles hierarchy with filtering rules for data sorting.
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