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Semi-automated Design of High-performance Digital Circuits with Xilinx FPGAs
Houška, David ; Dvořák, Vojtěch (oponent) ; Šťáva, Martin (vedoucí práce)
This master's thesis deals with sequential digital circuit design optimization concerning delay optimization. Two techniques commonly used for the optimization are described in the thesis – a brief description of the retiming technique and a more in-depth description of the pipelining technique. A form of abstraction of sequential digital circuits using Directed Acyclic Graphs (DAGs) was developed in the practical part of the thesis. This abstraction represents the circuit in a more manageable way for transformations. At the same time, a tool for semi-automatic digital circuit optimization using pipelining is introduced. This tool is compatible with Xilinx ISE Design Suite.
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Digital signal of pressure senzors processing using CPLD
Zátura, Michal ; Fedra, Zbyněk (oponent) ; Kováč, Michal (vedoucí práce)
The goal of this bachelor’s thesis is to design electronic part of the scanning system used to measure altitude. The electronic part is designed as module connected to the development platform XC2-XL. This module is realized like PCB. The principles of the signal processing of the signal from the pressure sensor MPXH6250, particular blocks of the designed module and principle of the barometrical altitude measuring are also described in this thesis. Thesis briefly informs about designing environment Xilinx ISE, VHDL language, the principle and the application of the pressure sensors, the structure of the programmable logic device CPLD and FPGA, the development platforms XC2-XL, the Xilinx Spartan-3 Starter Kit, the programmable logic devices CPLD Coolrunner-II XC2C256 and Spartan-3 XC3S200 FPGA used on the development platforms. The very important part is to design algorithm for processing the logarithm in the digital logic and it´s implementation in VHDL language.
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Semi-automated Design of High-performance Digital Circuits with Xilinx FPGAs
Houška, David ; Dvořák, Vojtěch (oponent) ; Šťáva, Martin (vedoucí práce)
This master's thesis deals with sequential digital circuit design optimization concerning delay optimization. Two techniques commonly used for the optimization are described in the thesis – a brief description of the retiming technique and a more in-depth description of the pipelining technique. A form of abstraction of sequential digital circuits using Directed Acyclic Graphs (DAGs) was developed in the practical part of the thesis. This abstraction represents the circuit in a more manageable way for transformations. At the same time, a tool for semi-automatic digital circuit optimization using pipelining is introduced. This tool is compatible with Xilinx ISE Design Suite.
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Digital signal of pressure senzors processing using CPLD
Zátura, Michal ; Fedra, Zbyněk (oponent) ; Kováč, Michal (vedoucí práce)
The goal of this bachelor’s thesis is to design electronic part of the scanning system used to measure altitude. The electronic part is designed as module connected to the development platform XC2-XL. This module is realized like PCB. The principles of the signal processing of the signal from the pressure sensor MPXH6250, particular blocks of the designed module and principle of the barometrical altitude measuring are also described in this thesis. Thesis briefly informs about designing environment Xilinx ISE, VHDL language, the principle and the application of the pressure sensors, the structure of the programmable logic device CPLD and FPGA, the development platforms XC2-XL, the Xilinx Spartan-3 Starter Kit, the programmable logic devices CPLD Coolrunner-II XC2C256 and Spartan-3 XC3S200 FPGA used on the development platforms. The very important part is to design algorithm for processing the logarithm in the digital logic and it´s implementation in VHDL language.
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