Národní úložiště šedé literatury Nalezeno 1 záznamů.  Hledání trvalo 0.01 vteřin. 
High-speed packet accumulation in FPGA
Beneš, David ; Pristach, Marián (oponent) ; Dvořák, Vojtěch (vedoucí práce)
This paper presents the concept of a digital circuit that has the potential to reduce the transmission overhead on the communication link between a high-speed network card with FPGA and a host PC for small packets. This circuit is specifically designed for the NDK platform developed by CESNET z.s.p.o., which is specified in the first chapter. The motivation for writing this thesis is presented in the second chapter, which is dedicated to the communication path between the host PC and the FPGA. The design of the resulting digital circuit and its testing is described in the final part of this thesis.

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