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Fault tolerant systems design automation
Lojda, Jakub ; Plíva, Zdeněk (oponent) ; Steininger, Andreas (oponent) ; Sekanina, Lukáš (vedoucí práce)
If a digital system is required to maintain a high level of reliability, it must withstand the presence of naturally-emerging failures. Many of such systems utilize Field Programmable Gate Arrays (FPGAs). One of the approaches to increase the system's reliability is the insertion of the so-called Fault Tolerance (FT) mechanisms. It is, however, a significant challenge to design systems to be FT. In this thesis, an approach is designed and researched, capable of automatically transforming an unhardened design into its FT version. The thesis emphasizes the generality of such a process, which allows for the reusability of the methods among various description formats, languages, and abstraction levels. This thesis describes the proposed method and its main aspects: the source code modification approaches, design strategies, and acceleration of FT parameters measurement. Last but not least, design flows that target the minimization of required measurements are proposed, which significantly accelerates the complete automated design of the FT system. Several cases were experimentally studied during the research presented in this thesis. Multiple circuits described in different languages were targeted with various reliability metrics to cover multiple scenarios. The first steps use a robot controller written in C++ as a target for evaluating the source code manipulations and the so-called critical bits representation of an FPGA design. After that, our C++ benchmark circuits were used instead of the robot controller. At first, a strategy based on the Multiple-choice Knapsack Problem (MCKP) was used to automatically select the most suitable hardening from available hardening schemes (e.g., Triple Modular Redundancy, or N-modular Redundancy). The proposed design strategy found a solution with 18% fewer critical bits while even lowering the design size overhead compared to the previous approach with the static allocation of FT mechanisms. After that, means of FT mechanism insertion were implemented for VHDL. VHDL benchmarks were also used with the MCKP strategy to find solutions with the best Median Time to Failure (a.k.a. t50). For the actual case study, circa 25% savings in the area were achieved compared to the reference design to which the FT mechanisms were assigned statically and manually. The method allows the user to constrain the available chip area and obtain the result optimal on reliability for this given area (under assumptions specified in the thesis). Also, system recovery was tested, which further improved the t50 results by 70%. Finally, a comprehensive case was studied on a real circuit, the FPGA reconfiguration controller. This presents a method of finding a Pareto-frontier of optimal designs considering multiple criteria (i.e., power consumption, size, and Mean Time to Failure - MTTF). The method exploits the principles of dynamic partial reconfiguration.
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Implementace struktur FPNN v C++
Skalník, Marek ; Lojda, Jakub (oponent) ; Krčma, Martin (vedoucí práce)
Tato práce se zabývá implementací simulátoru neuronových sítí v FPNN. V práci je rozebráno fungování neuronových sítí, implementace neuronových sítí v hardware a FPNN. Je zde rozebrán návrh implementace a samotná implementace simulátoru s využitím více vláken.
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VGA grabber pro FITkit
Lojda, Jakub ; Šimek, Václav (oponent) ; Vašíček, Zdeněk (vedoucí práce)
Práce pojednává o možnostech realizace VGA grabberu pro přípravek FITkit. Text je zaměřen na softwarové i hardwarové možnosti realizace. Úvod zavádí čtenáře do teorie dané problematiky. Následně práce uvádí několik možností realizace VGA grabberu a lehké zhodnocení variant. Druhá polovina práce je zaměřena na implementaci nejvýhodnější architektury VGA grabberu z uváděných variant a obsahuje stručné shrnutí poznatků o procesoru LPC4370 od firmy NXP a USB třídě UVC, na které je výsledná architektura založena. Závěr práce obsahuje stručné zhodnocení.
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USB keylogger
Lojda, Jakub ; Šimek, Václav (oponent) ; Vašíček, Zdeněk (vedoucí práce)
Práce se zabývá návrhem a praktickou realizací USB keyloggeru. Úvodní teoretická část je věnována sběrnici USB a popisu SD karet. Dále popisuje zvolený MCU Vinculum VNC2 a zacházení s dostupnými ovladači k tomuto obvodu. V dalších částech je podrobně rozebrán návrh a realizace firmware takového zařízení, včetně závěrečného měření propustnosti a identifikace nejslabších míst předloženého řešení. Následuje stručný popis výroby DPS. Součástí práce jsou i CD s kompletním zdrojovým kódem, schématem a rozložením DPS v programu Eagle, seznam potřebných součástek a fotografie hotového keyloggeru.
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Souborové systémy na různých typech paměťových médií
Bortlová, Pavlína ; Krčma, Martin (oponent) ; Lojda, Jakub (vedoucí práce)
Bakalářská práce se zabývá problematikou ukádání dat na různá paměťová média, konk- trétně na HDD, SSD, flash disky a SD karty. V teoretické části práce jsou rozebrány principy funkce paměťových médií a struktura ukládání dat prostřednictvím různých souborových systému. V praktické části byla měřena rychlost čtení a zápisu vybraných kombinací sou- borových systémů (FAT, NTFS, XFS, ext4, btrfs, exFAT, JFFS, F2FS) a paměťových médií (HDD, SSD, flash disk, sd karta).
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Fault tolerant systems design automation
Lojda, Jakub ; Plíva, Zdeněk (oponent) ; Steininger, Andreas (oponent) ; Sekanina, Lukáš (vedoucí práce)
If a digital system is required to maintain a high level of reliability, it must withstand the presence of naturally-emerging failures. Many of such systems utilize Field Programmable Gate Arrays (FPGAs). One of the approaches to increase the system's reliability is the insertion of the so-called Fault Tolerance (FT) mechanisms. It is, however, a significant challenge to design systems to be FT. In this thesis, an approach is designed and researched, capable of automatically transforming an unhardened design into its FT version. The thesis emphasizes the generality of such a process, which allows for the reusability of the methods among various description formats, languages, and abstraction levels. This thesis describes the proposed method and its main aspects: the source code modification approaches, design strategies, and acceleration of FT parameters measurement. Last but not least, design flows that target the minimization of required measurements are proposed, which significantly accelerates the complete automated design of the FT system. Several cases were experimentally studied during the research presented in this thesis. Multiple circuits described in different languages were targeted with various reliability metrics to cover multiple scenarios. The first steps use a robot controller written in C++ as a target for evaluating the source code manipulations and the so-called critical bits representation of an FPGA design. After that, our C++ benchmark circuits were used instead of the robot controller. At first, a strategy based on the Multiple-choice Knapsack Problem (MCKP) was used to automatically select the most suitable hardening from available hardening schemes (e.g., Triple Modular Redundancy, or N-modular Redundancy). The proposed design strategy found a solution with 18% fewer critical bits while even lowering the design size overhead compared to the previous approach with the static allocation of FT mechanisms. After that, means of FT mechanism insertion were implemented for VHDL. VHDL benchmarks were also used with the MCKP strategy to find solutions with the best Median Time to Failure (a.k.a. t50). For the actual case study, circa 25% savings in the area were achieved compared to the reference design to which the FT mechanisms were assigned statically and manually. The method allows the user to constrain the available chip area and obtain the result optimal on reliability for this given area (under assumptions specified in the thesis). Also, system recovery was tested, which further improved the t50 results by 70%. Finally, a comprehensive case was studied on a real circuit, the FPGA reconfiguration controller. This presents a method of finding a Pareto-frontier of optimal designs considering multiple criteria (i.e., power consumption, size, and Mean Time to Failure - MTTF). The method exploits the principles of dynamic partial reconfiguration.
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Fault tolerant systems design automation
Lojda, Jakub ; Plíva, Zdeněk (oponent) ; Steininger, Andreas (oponent) ; Sekanina, Lukáš (vedoucí práce)
If a digital system is required to maintain a high level of reliability, it must withstand the presence of naturally-emerging failures. Many of such systems utilize Field Programmable Gate Arrays (FPGAs). One of the approaches to increase the system's reliability is the insertion of the so-called Fault Tolerance (FT) mechanisms. It is, however, a significant challenge to design systems to be FT. In this thesis, an approach is designed and researched, capable of automatically transforming an unhardened design into its FT version. The thesis emphasizes the generality of such a process, which allows for the reusability of the methods among various description formats, languages, and abstraction levels. This thesis describes the proposed method and its main aspects: the source code modification approaches, design strategies, and acceleration of FT parameters measurement. Last but not least, design flows that target the minimization of required measurements are proposed, which significantly accelerates the complete automated design of the FT system. Several cases were experimentally studied during the research presented in this thesis. Multiple circuits described in different languages were targeted with various reliability metrics to cover multiple scenarios. The first steps use a robot controller written in C++ as a target for evaluating the source code manipulations and the so-called critical bits representation of an FPGA design. After that, our C++ benchmark circuits were used instead of the robot controller. At first, a strategy based on the Multiple-choice Knapsack Problem (MCKP) was used to automatically select the most suitable hardening from available hardening schemes (e.g., Triple Modular Redundancy, or N-modular Redundancy). The proposed design strategy found a solution with 18% fewer critical bits while even lowering the design size overhead compared to the previous approach with the static allocation of FT mechanisms. After that, means of FT mechanism insertion were implemented for VHDL. VHDL benchmarks were also used with the MCKP strategy to find solutions with the best Median Time to Failure (a.k.a. t50). For the actual case study, circa 25% savings in the area were achieved compared to the reference design to which the FT mechanisms were assigned statically and manually. The method allows the user to constrain the available chip area and obtain the result optimal on reliability for this given area (under assumptions specified in the thesis). Also, system recovery was tested, which further improved the t50 results by 70%. Finally, a comprehensive case was studied on a real circuit, the FPGA reconfiguration controller. This presents a method of finding a Pareto-frontier of optimal designs considering multiple criteria (i.e., power consumption, size, and Mean Time to Failure - MTTF). The method exploits the principles of dynamic partial reconfiguration.
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Dependability Assessment Based on SMC
Gajdošík, Róbert ; Lojda, Jakub (oponent) ; Strnadel, Josef (vedoucí práce)
The aim of this thesis is assessing dependability of computerized systems using modelling and simulation. After establishing basic nomenclature, research was performed on de- pendability metrics, fault taxonomy and dependability bolstering techniques. Afterwards, analytical solutions were explored to be used as a reference point. Next, multiple simulation tools were assessed and Uppaal SMC was chosen as the most suitable tool because of it’s timed automaton framework enriched with a query language and multiple Simulation Model Checking tools. Finally, systems describing multiple relevant situations were implemented and evaluated against both themselves and the analytically computed reference point.
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Prohlížeč obrázků pro desktopové prostředí KDE
Hladík, Daniel ; Lojda, Jakub (oponent) ; Krčma, Martin (vedoucí práce)
Protože fylozofie KDE je mít programy co nejvíce nastavitelné a rozšiřitelné, a to i za cenu vyšších nároků na systémové zdroje, existuje málo programů pro KDE, které by byli malé a efektivní. Proto se tato bakalářská práce zabývá vytvořením takového programu, který bude rychlý, efektivní a šetrný na zdroje. Program bude také mít módy prohlížení, které se v prohlížečích obrázků pro KDE nevyskytují.
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