National Repository of Grey Literature 877 records found  beginprevious859 - 868next  jump to record: Search took 0.00 seconds. 
Pasive coherent radiolocator - FPGA implementation of signal accelerator
Heřmánek, Antonín ; Kvasnička, M.
The paper presetns the implemantation of the HW architecture based on FPGA for CAF computation, which will by suitable for future real-time PCL systems.
Rekonfigurovatelná architektura pro zpracování obrazu s podporou rychlého modelování v Simulinku
Schier, Jan ; Kovář, Bohumil ; Zemčík, P. ; Herout, A. ; Beran, V.
A novel concept of an embedded image processing architecture is presented in the paper. This architecture is based on an interconnection of a programmable logical chip with a digital signal processor. Both these devices have characteristic that complement well each other for broad-class of data-intensive image-and video-processing tasks. For efficient utilization of such device, a multi-level configuration system is needed. The paper describes both the HW and SW architecture of the system.
Model přenosového systému záchranářského robotu Orpheus
Mazanec, Tomáš ; Heřmánek, Antonín ; Matoušek, Rudolf
The robotic platform Orpheus is a top-class reconnaissance system controlled by an innovative technology called telepresence.The transmissions system of the robot is very critical part, because it must provide short robot response time, while serving wide band video signal to the operator. Wi-Fi technology can handle both parameters, but it struggles with poor reliability in situations without line of sight between the robot and the operator's transmitter antenna. An article deals with a model in Matlab.
Podpora dynamické rekonfigurace pro AVR
Honzík, Petr
This paper presents a software core for an universal econfiguration system-on-a-programmable chip platform based on Atmel AT94K FPSLIC with an external FLASH memory. The AVR core controls basic functions that together with the FPSLIC platform creates a transparent infrastructure for software-driven FPGA reconfiguration.

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