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Development Board for 32-bit Microcontroller Atmel AT91SAM9261
Demín, Martin ; Slaný, Karel (referee) ; Šimek, Václav (advisor)
Vestavený hardware je velice populární v této době. Proto jsme se rozhodli vytvořit desku s mikrokontrolérem AT91SAM9261 spolu so standartným a nestandartným hardwarem. Standartným, běžným by se dal nazvat port LAN alebo audio vstup-výstup. Nestandartným, špecialním by mohl být obvod FPGA firmy Xilinx o velikosti 200k. Toto dovoluje využít zažízení v oblastech, kde výpočetní síla obyčejnýho CPU již není dostačující.
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Logic analyzer module based on PCIe card
Juřík, Tomáš ; Macho, Tomáš (referee) ; Valach, Soběslav (advisor)
The goal of this bachelor's thesis is to implement simple FPGA-based logic analyzer connected to PCI-Express bus. Furthermore four counters are implemented to generate testing dataset. This thesis describes a fundamental priciple and use of logic analyzer. An overview of Spartan-3 PCI Express Starter Kit development board and Xilinx Spartan-3 field-programmable gate array anrchitecture is given. Stages of logic analyzer development are detailed as well.
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Programme module of RS232 format receiver in FPGA
Hrubý, Jiří ; Kolouch, Jaromír (referee) ; Prokeš, Aleš (advisor)
The bachelor’s thesis describes program module of RS232 format receiver. The program is written in programming language VHDL for circuits FPGA from Xilinx corporation. Within the frame of the work the simulation and implementation of data receiver was solved. Simulation and implementation was performed by means of the development system XILINX ISE WebPACK.
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Sample assignments in VHDL
Huzlík, Petr ; Macho, Tomáš (referee) ; Holek, Radovan (advisor)
This bachelor’s study connects on semestral project and is focused on VHDL language and FPGA and CPLD circuits by Xilinx. The aim of this study is to describe how to work with profossional design tool WebPack. Documents detaily describes how to create new project on advanced level - with emphasis on methodiology and examples from practice in VHDL lenguage.
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Microprocessor system IP core generator
Kerber, Rostislav ; Tošovský, Petr (referee) ; Kubíček, Michal (advisor)
This master’s thesis deal’s with VHDL programming language, ISE Webpack design system and PicoBlaze microprocessor. The thesis describes essentials of VHDL programming language and its application. A simple introduction to ISE Webpack design environment is given. The thesis describes common peripherals and the PicoBlaze processor is described too, including its parameters and implementation aspects. Finally the thesis describes IP generator for generating complex FPGA design including Picoblaze processor.
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Partial reconfiguration methods based on programmable structures
Kolář, Jan ; Kváš, Marek (referee) ; Valach, Soběslav (advisor)
This master's thesis dissertates of partial reconfiguration methods based on programmable structures. In theoretical part it deals with difference and modular-based method of Xilinx's FPGAs Partial reconfiguration. Options of both reconfiguration techniques were written for Spartan 3, Virtex II, Virtex 4 and Virtex 5 processors. Diference-based method was in practical part tested on Spartan 3E Starter Kit and modular-based on ML501 board. All configuration bitstreams are included on CD. Xilinx Inc. provided all needed software tools such as ISE9.2i and PlanAHEAD.
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Implementation of software radio into FPGA
Šrámek, Petr ; Maršálek, Roman (referee) ; Prokeš, Aleš (advisor)
The common objective of this project is implementation of software defined radio (SDR) into FPGA. The text contains review and comparison of several hardware concepts intended for SDRs implementation then the methods for digital implementation of various components of radios as the filters, mixers and others are mentioned. Part of the text introduces used hardware platform and describes software support for designing, simulations and implementation into hardware. Significant part of project describes complex of external hardware components as filter, amplifier and control panel designed and built within the project realization. But the main part of project demonstrates design of the software solution of radio receiver. There is specified architecture of radio for FM broadcast receiving, next the more complex systems with carrier recovery algorithm are presented. These systems are able to work with AM, BPSK and QPSK modulations. It is possible to implement all these receivers into hardware and verify their operation. The practical laboratory theme has been outlined within the project run.
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Methods for quadrature modulator imbalance compensation
Povalač, Karel ; Valenta, Václav (referee) ; Maršálek, Roman (advisor)
Quadrature modulator (demodulator) is used in transmitting (receiving) part of many devices. Unwanted imbalance can influence amplitude, phase or DC offset of modulator (demodulator). Correction of imbalance was a main subject of thesis. Simulations of these methods were created in MATLAB and results were compared. Basics of methods were implement on programmable logic field by program Xilinx ISE. Development kit V2MB1000 with analogue board Memec P160 was chosen for this purpose. In the last part were compare simulation results with practical measurement.
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Digital predistorters for amplifier linearization
Kroužil, Miroslav ; Valenta, Václav (referee) ; Maršálek, Roman (advisor)
In this work I describe digital predistortion in baseband used for amplifier linearization. Non-linearity is one of the worst disadvantages of Power amplifiers and decreasing of its is useful from many reasons. Work examines system which contains: Data source, which is represented by QPSK or OFDM modulator, predistorter, Power amplifier (model of non-linearity) and unit used to update coeficients for predistorter adaptation. System is simulated in MATLAB and Xilinx (simulation by ModelSim). Results are compared, described and commented.
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FPGA core for data displaying on computer monitor using VGA port
Pišl, Adam ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
The aim of this project is to perform the study of a driver for controlling computer monitor using VGA port. The driver is based on FPGA which is used to generate VGA signals. The main purpose of the project is to design a hardware core for gate array which can be used as part of some complex FPGA design to provide a comfortable user interface. The project describes the main part of the VGA driver – module for generating control signals and module for displaying text information that is sent from a PC via serial port interface.
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