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Acceleration of Methods for Searching Palindroms and Repetitive Structures
Voženílek, Jan ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
Genetic information of all living organisms is stored in DNA. Exploring of its structure and function represents an important area of research in modern biology. One of the interesting structures occurring in DNA are palindromes. Based on the research they are expected to play an important role in interpreting the information stored in DNA, because they are often observed near important genes. Palindromes searching is complicated by the presence of mutations (changes in sequences of DNA elements), which increases the time complexity of algorithms. Therefore it is reasonable to study their parallelization and acceleration. The objective of this work is a study of palindromes searching methods and acceleration architecture design. The hardware unit implemented in a chip with FPGA technology placed on ml555 board can speed up the calculation up to 6 667 times in comparison with the best-known software method relying on suffix arrays.
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Asymmetric-Key Cryptography in Embedded Systems
Záhorský, Matej ; Kula, Michal (referee) ; Nosko, Svetozár (advisor)
Účelom tejto práce je prieskum a implementácia existujúceho asymetrického kryptografického algoritmu v FPGA a vyhodnotenie jeho výkonu. Prvá kapitola sa zameriava na vstavané systémy a FPGA, pričom popisuje ich štruktúru a použitie. V druhej kapitole je porovnanie kryptografických algoritmov a ich vlastností, ktoré umožňujú ich použitie vo vstavaných systémoch. Fázy návrhu a implementácie v tomto projekte popisujú a implementujú riešenie, ktoré zahŕňa výber a integráciu podpisovacieho algorithmu v FPGA. Dodatočné optimalizácie na zvýšenie výkonu sú taktiež naimplementované vo forme hardvérovej akcelerácie, ktoré sú zároveň porovnané s pôvodným algoritmom v kapitole vyhodnotenia.
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Acceleration of Particles Tracking on CBM Experiment
Roth, Michael ; Kolář, Martin (referee) ; Musil, Petr (advisor)
The focus of this work is to research various methods of particle track reconstruction in the CBM experiment, and the problem of hardware acceleration of these methods. The advantages and disadvantages of the extended methods were discussed and a reconstruction method based on cellular automata and Extended Kalman filters was selected for further study. In particular, the thesis details the development of a simulation model suitable for generating test data to facilitate the implementation of the selected tracking algorithm, which was subsequently sped up using distributed computing methods. Two different particle simulation models and a reconstruction algorithm were implemented, with the reconstruction algorithm offering up to 800 per cent speed up factor in respect to the sequential algorithm and up to four orders of magnitude lower memory complexity.
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Design and Development of a Hardware Accelerator of Demanding Computations with Multiple FPGAs
Zach, Petr ; Levek, Vladimír (referee) ; Šťáva, Martin (advisor)
This master's thesis focuses on the design and development of a printed circuit board with multiple FPGA connected by a high-speed bus. The goal of the project is to design and develop a board that will be able to accelerate calculations of demanding algorithms in various applications such as image processing, machine learning, cryptography, and other algorithms from the field of digital signal processing. The first chapter introduces the field of hardware acceleration, focusing on the characteristics of chips used in this field and comparing them. The second chapter examines the possibilities of hardware accelerators on the market. The third chapter describes the conceptual design of a custom hardware accelerator. First, the conceptual design is introduced, explaining the structure of the device. Subsequently, the design of the prototype of this device and its implementation on a PCB are described in detail.
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Acceleration of Particles Tracking on CBM Experiment
Roth, Michael ; Kolář, Martin (referee) ; Musil, Petr (advisor)
The focus of this work is to research various methods of particle track reconstruction in the CBM experiment, and the problem of hardware acceleration of these methods. The advantages and disadvantages of the extended methods were discussed and a reconstruction method based on cellular automata and Kalman filters was selected for further study. In particular, the thesis details the development of a simulation model suitable for generating test data to facilitate future implementation of the selected tracking algorithm. Two different particle simulators have been developed and will be used in the following work to calculate the prediction step of the extended Kalman filter and to test the quality of the implemented reconstruction method.
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Hardware Acceleration Demo on the Pynq Z2 Board
Vosyka, Pavel ; Kekely, Lukáš (referee) ; Kořenek, Jan (advisor)
The work deals with a hardware acceleration on the Zynq platform with Pynq technology. Three examples demonstrating hardware acceleration were designed for teaching purposes. The effort was to make examples as simple as possible to make them easy to understand. Hardware accelerators are implemented in VHDL language and driven by implemented Python application. The examples were successfully implemented and evaluated.
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Accelerating an Application for DDoS Mitigation
Vojanec, Kamil ; Kekely, Lukáš (referee) ; Kučera, Jan (advisor)
This thesis focuses on optimizing and accelerating an application used for mitigating Denial of Service attacks. The goal is to analyze the existing implementation of DDoS Protector and to identify components which are suitable for optimization or hardware acceleration. Based on the analysis, improved algorithms and data structures utilizing the DPDK open-source framework are designed together with a proposal to offload certain computation elements into hardware using the RTE Flow library. The result of this thesis is a set of modules and an implementation of classification components intended to be used within the DDoS Protector application. The resulting components are then properly tested. Finally, the performance results of the original and new implementations are compared. The application shows as much as five-times improvement in terms of packet rate when using 256 classification rules.
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Acceleration of Open vSwitch in DPDK
Vodák, David ; Kučera, Jan (referee) ; Martínek, Tomáš (advisor)
Virtual switch is a software that connects virtual machines to the internet, which makes it a crucial part of virtualization on servers. Nevertheless, it can be rather ineffective when it comes to high speed traffic, since it switches all frames in the software. This thesis is about hardware acceleration of the virtual switch called Open vSwitch. The acceleration prototype, which is the goal of this thesis, is based on the RTE flow interface, the SR-IOV standard, and Intel PAC N3000 card. In the scope of this master's thesis, all necessary technologies were described and the acceleration prototype was designed, implemented, and tested. Results of executed measurements indicate increased throughput when rules of the acceleration prototype were offloaded to hardware.
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Unified verification environment for digital part of automotive mixed-signal integrated circuits
Petráš, Samuel ; Dvořák, Vojtěch (referee) ; Prokop, Roman (advisor)
This thesis is concerned with unified verification environment for the verification of small designs of the digital part of integrated circuits with mixed signals. By unified verification environment is meant an environment suitable for both simulation and emulation. The first chapter describes the current verification methods of such designs. The second chapter presents the requirements that emulation places on the verification environment implemented according to the Universal Verification Methodology (UVM) and the attached implementation of proposed environment. The third chapter contains practical knowledge gained during the implementation of the unified verification environment, problems and their solutions, as well as several comparisons between simulation and emulation.
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Hardware-Accelerated Cryptography For Software-Defined Networks
Cíbik, Peter
This paper presents a Software-Defined Network (SDN) cryptographic solution targetedon high-speed smart Network Interface Cards (NICs) with an FPGA chip. This solution providesa fast alternative method to develop network-oriented data processing cryptography applications foran accelerator. A high-level programming language – Programming Protocol-independent PacketProcessor (P4) – is used to avoid a complex and time-consuming hardware development. The solutionconsists of two main parts: a library of mainly used cryptographic primitives written in VHSICHardware Description Language (VHDL) i.e. a symmetric cipher (AES-GCM-256), a hash function(SHA-3), a SHA-3-based Hash-based Message Authentication Code (HMAC), a digital signaturescheme (EdDSA) and a post-quantum digital signature scheme (Dilithium), and a compiler P4/VHDLwith the support for these cryptographic components as external objects of P416.
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