National Repository of Grey Literature 127 records found  beginprevious21 - 30nextend  jump to record: Search took 0.11 seconds. 
Generating Code of Optimised Mathematical Operations
Beneš, Vojtěch ; Horáček, Petr (referee) ; Čermák, Martin (advisor)
Bachelor's thesis deals with creating a simple programming language for working with mathematical operations. Main point of the thesis is to create a compiler of this language, which is using MMX technology to generate instructions of an assembler code. The optimized code generation is based on modified algorithm of context generation.
Grammar Systems Applied to Compilation
Reš, Jakub ; Klobučníková, Dominika (referee) ; Meduna, Alexandr (advisor)
The main goal of this work is to design a method of constructing a compiler based on grammar systems that allows it's user to by able to combine any existing construction methods. Solution of this problem lies in utilization of cooperating distributed grammar systems. The principle of dividing compiler into sequentially cooperating components was used by this thesis. So we have a construction of smaller, narrowly specified units that are able to pass control to each other and together analyze complex languages. Each of these components is using one of the existing methods of analysis and any way of it's implementation. Benefit of this thesis is the design of construction method using principle of grammar systems, that allows us to use combination of any existing methods and brings overall higher generative power, and showing a possible way of using this method.
Retargeting of LLVM Platform for Motorola 68000 Microprocessor
Blahož, Vladimír ; Husár, Adam (referee) ; Hruška, Tomáš (advisor)
This bachelor's thesis deals with general questions of compilers, describes the Low-Level Virtual Machine platform and its modification options. Furthermore it concerns about principles of Motorola 68000 architecture and implementation of its instruction set for the LLVM platform.
Optimalization of an Agent Code
Hemala, Luboš ; Kočí, Radek (referee) ; Zbořil, František (advisor)
This work continues in an effort to improve the compiler of the AHLL agent language. The main focus is to integrate optimizations that would reduce the size of the target ALLL code, therefore global register allocation by graph coloring is implemented in this version. Some changes to the language are introduced as well, but which impose a more complicated compiler structure. The overall results of the new compiler then indicate a 35 % decrease in the size of the code on average for the evaluated complex agents.
Regulated Syntax-Directed Translation
Dvořák, Tomáš ; Kocman, Radim (referee) ; Meduna, Alexandr (advisor)
This thesis deals with formal and syntax directed translation. This thesis contains theoretical part, which defines regular, context free, context sensitive and recursively enumerable languages a grammar. There are given examples of grammars which are able to generate languages that are not context free. Covered by this thesis are matrix grammars, random context grammars and programed grammars. Researched are also finite, pushdown, deep and regular automata, transducers and their part within format syntax directed translation. This project also defines regular transducers based as regulated automata. Thesis defines regulated methods of syntax analysis based on predictive parsers. These methods cover analysis of studied regulated grammars. The final part of this thesis describes new language capable of effective description of these grammars and compiler producing parser code for these grammars written in this new language and their graphical analyzer.
Generic Obfuscation on the Bytecode Level
Kollát, Samuel ; Křoustek, Jakub (referee) ; Ďurfina, Lukáš (advisor)
This work contains definition of obfuscation and methods of obfuscation. It is followed by description of LLVM Project and its suitability for obfuscation on the bytecode level for purpose of targeting different architectures. The core of the work is formed by detailed design of obfuscation methods aiming towards their implementation in back-end of LLVM compiler. Closing section is dedicated to verification of implemented functionality on different architectures by automated testing.
Parsing Based on Grammar Systems
Sedmík, Adam ; Klobučníková, Dominika (referee) ; Meduna, Alexandr (advisor)
This thesis is focused on grammar systems and syntax analysis. Thesis introduces cooperating distributed and parallel communicating grammar systems. Based on knowledge of grammar systems, new grammar system is introduced. This grammar system focuses on modularization of syntax analysis. Shown are two methods of syntax analysis, recursive descent parsing and precedence parsing. Grammar systems introduced are demonstrated on syntax analysis of custom programming language.
Compiler for Multicore Systems
Barteček, Jakub ; Přikryl, Zdeněk (referee) ; Masařík, Karel (advisor)
This bachelor´s thesis deals with parallel processing programs at the platform EdkDSP. The most important parts of this thesis are an analyzation of the target platform and a design of the translator. The design is aimed at translation of the OpenMP pragmas to a multithreaded code and a transformation of the specific types of cycles. The translator was implemented using the framework ROSE compiler and than tested.
Specialized Interpreter of JavaScript Language
Borůvka, Jan ; Rychnovský, Lukáš (referee) ; Peringer, Petr (advisor)
The aim of this master's thesis is to design and implement JavaScript interpreter which is designed for purposes of avoiding obfuscation code of various types of computer viruses. This master's thesis also comprises a detailed view into the inner mechanism of the ECMAScript standard.
Instruction Scheduler of C Compiler for VLIW Architecture
Mináč, Tomáš ; Trmač, Miloslav (referee) ; Hruška, Tomáš (advisor)
This bachelor thesis discusses about VLIW processor architecture and about the part of the compiler which is designed for instruction scheduling. It describes LLVM compiling platform, especially those parts which are important to create new schedulling pass for VLIW architecture. Creation schedulling pass is also a result of this work. Futhermore, test results of newly Scheduling pass are described. Test was conducted on VEX architecture.

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