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LDPC codes
Hrouza, Ondřej ; Šedý, Jakub (referee) ; Šilhavý, Pavel (advisor)
The aim of this thesis are problematics about LDPC codes. There are described metods to create parity check matrix, where are important structured metods using finite geometry: Euclidean geometry and projectice geometry. Next area in this thesis is decoding LDPC codes. There are presented four metods: Hard-Decision algorithm, Bit-Flipping algorithm, The Sum-Product algorithm and Log Likelihood algorithm, where is mainly focused on iterative decoding methods. Practical output of this work is program LDPC codes created in environment Matlab. The program is divided to two parts -- Practise LDPC codes and Simulation LDPC codes. The result reached by program Simulation LDPC codes is used to create a comparison of creating and decoding methods LDPC codes. For comparison of decoding methods LDPC codes were used BER characteristics and time dependence each method on various parameters LDPC code (number of iteration or size of parity matrix).
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Software for learning support of error-correcting codes
Petrik, Ján ; Vlček, Lukáš (referee) ; Burda, Karel (advisor)
This Bachelor thesis is mainly focused on issues of the chosen error correcting codes (ECC) and their demonstrative. Goal of this work is help to understand ECC to readers, easy and reasonable form. We can find here a lot of illustrative tables and figures for better understanding how codes works. Every section constains one code and mostly is filled by code securing and code decoding. For every section interactive Aplet and program for experimental uses were created.
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Data transmition security with Reed-Müller codes
Hrouza, Ondřej ; Burda, Karel (referee) ; Němec, Karel (advisor)
The aim of this work is to propose a Reed-Muller code that secure data transfer to t = 4 independent errors, the information rate R ? 0,5 and for this code to produce a detailed proposal for implementation of the codec. In order to implement this proposal, it is necessary to familiarize themselves with the basic properties Reed-Muller codes. To understand the function of codec Reed-Muller code is in this thesis analyzed the process of encoding and decoding, which is based on a method of using the majority logic. For the design of codec, which consists of encoder and decoder, are used programmable logic circuits FPGA. These circuits are programmed in VHDL language, when for the design source codes is used Xilinx ISE 10.1. In thesis is examined in detail the structure and function of the encoder and decoder chosen Reed-Muller code and there are presented parts of the proposed source codes. Verify the functional ability of the codec is achieved by simulation in program ModelSim SE 5.7f. The simulation results together with the another proposal realization are output of this work.
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Meaning of verbs for spatial orientation of children aged 45 - 60 months
Landrová, Lenka ; Mošna, František (referee) ; Kaslová, Michaela (advisor)
Diploma thesis deals with verbal communication of children aged 45 - 60 months within the context of dynamic spatial orientation. Verbs describing area variances are commonly used in mathematic word problems at primary schools. The diploma thesis monitors the possibilities / difficulties of preschool education to prepare children to manage such situations. The methods used in the research are observation and lab experiment. The purpose of the work is to learn: a, which verbs, or groups of verbs describing area variances are part of passive / active language vocabulary of pre-school children b, under which circumstances children react to the verbs stated above, and how they understand them c, how children are able to code the verbs grafically / decode the graphic code. The communication connected with dynamic spatial orientation is presented at three levels: at the level of manipulation, kinesis and the graphic level.
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Translation of x86 Binary Code To a High-Level Language
Jurík, Marián ; Křivka, Zbyněk (referee) ; Kolář, Dušan (advisor)
The purpose of this MSc thesis is to create design and implementation of program for translation of x86 binary code to a high-level programming language. There is described PE file format for executables used in MS Windows operating systems in the first part of work. This document contains general information about instruction set IA-32, especially a way of decoding binary code to assembly language. There are described typical program constructions, which are being used in compilers. Design of creation high-level programming language was inspired by existing programming languages. Conclusion is made about advantages and disadvantages of approach used in this thesis.
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Automated firmware upload of many AVR microcontrollers over SPI bus
Boštík, Jiří ; Lattenberg, Ivo (referee) ; Hanák, Pavel (advisor)
The aim of this work is to construct a circuit for automated programming more microcontrollers Atmel AVR through the SPI bus and to devise and execute demonstration plant that will be able to automate this task, at least partially, therefore, ideally without human intervention, one programmer to load the firmware into more microcontrollers. The theoretical part describes the components that are used in the work, the description of their functionality and usability. For switching between microcontrollers we have a choice of two options. The first option is monitoring of the signal "reset", which is a simpler variant of SPI, or decoding the Atmel instructions. Thanks to the simplicity and practicality of the work will be used to monitoring of the signal of the "reset". For a better understanding in the work described how the whole problem will be work. They will describe each of the steps and for better orientation will be the block diagram too, which represents the most important part of the work. The practical part focuses on the practical testing of the proposed solution. In order to monitor the signal of the "reset" first we have to coordinate asynchronous counter with signal "reset" it to properly reply to a downward edge. Next we bring from the asynchronous counter BCD code with which the decoder switches to each of the microcontrollers using the switching transistors and then they are gradually programmed. Work will be used the programmer AVR Dragon, for which it will be used by the batch file for atprogram.exe, which is a standard part of Atmel Studio 6. In the work will be at least a partial test of the proposed problem to contact layer the field.
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BCH codes
Frolka, Jakub ; Šilhavý, Pavel (referee) ; Šedý, Jakub (advisor)
The work deals with data security using BCH codes. In the work are described BCH codes in binary and non-binary form, and their most important subclass RS codes. Furthermore, this work describes the method of decoding Peterson-Gorenstein-Zierl, Berlekamp- Massey and Euclidean algorithm. For the presentation of encoding and decoding process, the application was created in Matlab, which has two parts – Learning BCH codes and Simulation of BCH codes. Using the generated application performance of BCH codes was compared at the last part of the work.
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Comparison of decoding algorithms of Reed-Solomon code
Šicner, Jiří ; Krajsa, Ondřej (referee) ; Šilhavý, Pavel (advisor)
The work deals with the encoding and decoding of Reed-Solomon codes. There is generally described algebraic decoding of Reed-Solomon codes, and then described four methods of decoding, namely Massey-Berlekamp algorithm, Euclidean algoritus, Peterson-Gorenstein-Zierler algorithm and the direct method. These methods are then compared, and some of them are implemented in Matlab.
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Turbo-convolution and turbo-block codes
Šedý, Jakub ; Krajsa, Ondřej (referee) ; Šilhavý, Pavel (advisor)
The aim is to explain the Turbo convolutional and block turbo codes and decoding the secure message. The practical part focuses on the design of a demonstration program in Matlab. The work is divided into four parts. The first two deal with theoretical analysis of coding and decoding. The third section contains a description created a demonstration program that allows you to navigate the process of encoding and decoding. The fourth is devoted to simulation and performance of turbo codes.
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