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National Repository of Grey Literature 12 records found  previous11 - 12  jump to record: Search took 0.01 seconds. 
System of Internal Buses for Chips with FPGA Technology
 Málek, Tomáš ; Kořenek, Jan (referee) ; Martínek, Tomáš (advisor)
This thesis deals with design and implementation of interconnection bus system for chips with FPGA technology. The system ensures both communication between internal components on a chip and their communication with other computer elements which are mapped to the host system memory. The buses are high-speed, full duplex and packet-oriented and their architecture is based on tree topology. The data width is configurable, individually for every bus part. Due to this feature, it is possible to build uniform hierarchical system of internal buses with different speed that interconnects differently fast components. Proposed interconnection system was implemented in VHDL language and it is utilized in the Liberouter project which is the part of CESNET research intention Programable Hardware.
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Logic analyzer module based on PCIe card
 Juřík, Tomáš ; Macho, Tomáš (referee) ; Valach, Soběslav (advisor)
The goal of this bachelor's thesis is to implement simple FPGA-based logic analyzer connected to PCI-Express bus. Furthermore four counters are implemented to generate testing dataset. This thesis describes a fundamental priciple and use of logic analyzer. An overview of Spartan-3 PCI Express Starter Kit development board and Xilinx Spartan-3 field-programmable gate array anrchitecture is given. Stages of logic analyzer development are detailed as well.
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National Repository of Grey Literature : 12 records found   previous11 - 12  jump to record:
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