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Studium dielektrické relaxace v základních materiálech DPS a v izolacích kabelů
Ježík, Jan ; Brzobohatý, Jaromír (oponent) ; Běťák, Petr (vedoucí práce)
Tato práce studuje relaxační polarizace v některých dielektrických částech testeru UNISPOT S40 firmy UNITES Systems a.s. Relaxační polarizace v základních materiálech desek plošných spojů a v izolacích kabelů testeru jsou totiž příčinou nežádoucího zpomalení několika testovacích kroků. Relaxační vlastnosti vybraných základních materiálů DPS a vybraných kabelů jsou zkoumány metodou dielektrické relaxační spektroskopie ve frekvenční oblasti a metodou měření polarizačního respektive depolarizačního proudu.
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Ekologický návrh v elektronice - legislativa a nástroje pro optimalizaci
Chlup, Marian ; Brzobohatý, Jaromír (oponent) ; Szendiuch, Ivan (vedoucí práce)
Předkládaná diplomová práce se zabývá problematikou ekologického návrhu a optimalizace elektrotechnických výrobků. Teoretická část popisuje problematiku ekodesignu, legislativu a nástroje pro hodnocení. Praktická část je zaměřena na vytvořený software a na hodnocení a porovnání elektrotechnických výrobků. Byly analyzovány tři flash disky, které jsou běžně používány. U těchto flash disků byla provedena analýza obalů a tyto obaly byly následně hodnoceny softwarem a porovnávány. V poslední části je popsána problematika dostupnosti potřebných informací.
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Circuits for Analog Signal Processing Employing Unconventional Active Elements
Khatib, Nabhan ; Brzobohatý, Jaromír (oponent) ; Zaplatílek,, Karel (oponent) ; Biolek, Dalibor (vedoucí práce)
The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.
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Digitálně řízené analogové funkční bloky a systémy
Brich, Tomáš ; Brzobohatý, Jaromír (vedoucí práce)
Úkolem této disertační práce je zaměřit se na princip fungování základních analogových obvodů a stanovit, které parametry těchto bloků lze řídit pomocí externího digitálního systému. Dále jsou předvedeny ukázky některých digitálně řízených analogových obvodů a je provedena jejich analýza. Některé obvody byly realizovány a práci jsou uvedeny výsledky jejich měření.
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Techniky návrhu nízkonapěťových proudových konvejorů
El Dbib, Issa ; Brzobohatý, Jaromír (vedoucí práce)
This thesis work discusses the low-voltage current-mode CCII analog circuits and their various aspects. The need of high speed, high performance, low power circuits because of the advent of the portable electronic and mobile communication systems and difficulties faced in achieving that in today, this need for high performance LV circuits give encourages the analog designers to look for new circuit architectures, and new LV techniques. Self cascode and bulk-driven techniques can help to produce efficient LV circuits with reduced power supply restrictions are explained, some of the basic building blocks such as current mirrors, differential pairs structures capable to operate in LV are explored and discussed. The basic device level techniques also play important role in the design of smarter and efficient circuits; some of those techniques have also been discussed here. Designing CCII using low voltage techniques is the core part in this thesis, their advantages are discussed here and a comparison with the conventional mode circuits has been presented, The principle and the implementation of the most common CCII-based operational amplifier circuits has been described.
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Nízkopříkonové emulátory prvků vyššího řádu
Teska, Tomáš ; Brzobohatý, Jaromír (oponent) ; Biolek, Dalibor (vedoucí práce)
Diplomová práce je zaměřena na emulaci prvků vyšších řádů pomocí transformačních mutátorů, které v roce 1971 popsal Leon Chua. V práci je uveden postup návrhu mutátorů od jejich matematického popisu až po syntézu konkrétních zapojení. Obvodová řešení jsou založena na využití moderních obvodových principů s cílem dosažení optimálních výsledných parametrů. Mutátory jsou realizovány v podobě sady osmi inkrementálních modulů. Jejich kaskádním spojováním je pak možné emulovat libovolné prvky z periodické tabulky prvků vyšších řádů. Navržená řešení jsou testována pomocí počítačových simulací a ověřována měřeními.
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Residue Number System Based Building Blocks for Applications in Digital Signal Processing
Younes, Dina ; Brzobohatý, Jaromír (oponent) ; Vlček, Čestmír (oponent) ; Šteffan, Pavel (vedoucí práce)
This doctoral thesis deals with designing residue number system based building blocks to enhance the performance of digital signal processing applications. The residue number system (RNS) is a non-weighted number system that provides carry-free, parallel, high speed, secure and fault tolerant arithmetic operations. These features make it very attractive to be used in high-performance and fault tolerant digital signal processing (DSP) applications. A typical RNS system consists of three main components; the first one is the binary to residue converter that computes the RNS equivalent of the inputs represented in the binary number system. The second component in this system is parallel residue arithmetic units that perform arithmetic operations on the operands already represented in RNS. The last component is the residue to binary converter, which converts the outputs back into their binary representation. The main aim of this thesis was to propose novel structures of the basic components of this system in order to be later used as fundamental units in DSP applications. This thesis encloses improving and designing novel structures of these components, simulating and verifying their efficiency via FPGA implementation. In addition to suggesting novel structures of basic RNS components, a detailed study on different moduli sets that compares and determines the most efficient one for different dynamic range requirements is also presented. One of the main outcomes of this thesis is concluding and verifying the main condition that should be met when choosing a moduli set, in order to improve the timing performance of a DSP application. An RNS-based image processing application is also proposed. Its efficiency, in terms of timing performance and power consumption, is proved via comparing it with a binary-based one. Finally, the main considerations that should be taken into account when choosing to use the binary number system or RNS are also discussed in details.
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Residue Number System Based Building Blocks for Applications in Digital Signal Processing
Younes, Dina ; Brzobohatý, Jaromír (oponent) ; Vlček, Čestmír (oponent) ; Šteffan, Pavel (vedoucí práce)
This doctoral thesis deals with designing residue number system based building blocks to enhance the performance of digital signal processing applications. The residue number system (RNS) is a non-weighted number system that provides carry-free, parallel, high speed, secure and fault tolerant arithmetic operations. These features make it very attractive to be used in high-performance and fault tolerant digital signal processing (DSP) applications. A typical RNS system consists of three main components; the first one is the binary to residue converter that computes the RNS equivalent of the inputs represented in the binary number system. The second component in this system is parallel residue arithmetic units that perform arithmetic operations on the operands already represented in RNS. The last component is the residue to binary converter, which converts the outputs back into their binary representation. The main aim of this thesis was to propose novel structures of the basic components of this system in order to be later used as fundamental units in DSP applications. This thesis encloses improving and designing novel structures of these components, simulating and verifying their efficiency via FPGA implementation. In addition to suggesting novel structures of basic RNS components, a detailed study on different moduli sets that compares and determines the most efficient one for different dynamic range requirements is also presented. One of the main outcomes of this thesis is concluding and verifying the main condition that should be met when choosing a moduli set, in order to improve the timing performance of a DSP application. An RNS-based image processing application is also proposed. Its efficiency, in terms of timing performance and power consumption, is proved via comparing it with a binary-based one. Finally, the main considerations that should be taken into account when choosing to use the binary number system or RNS are also discussed in details.
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