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Samodlážditelné simplexy
Safernová, Zuzana ; Cibulka, Josef (referee) ; Matoušek, Jiří (advisor)
In the present work we study tetrahedral k-reptiles. A d-dimensional simplex is called a k-reptile if it can be tiled in k simplices with disjoint interiors that are all congruent and similar to S. For d = 2, triangular k-reptiles exist for many values of k and they have been completely characterized. On the other hand, the only simplicial k-reptiles that are known for d 3 have k = md, where m 2 (Hill simplices). We prove that for d = 3, tetrahedral k-reptiles exist only for k = m3. This partially confirms the Hertel's conjecture, asserting that the only tetrahedral k-reptiles are the Hill tetrahedra. We conjecture that k = md is necessary condition for existence of d-dimensional simplicial k-reptiles, d > 3.
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Věty Hellyho typu a zlomkového Hellyho typu
Tancer, Martin ; Kaiser, Tomáš (referee) ; Matoušek, Jiří (advisor)
A simplicial complex is d-representable if it is the nerve of a collection of convex sets in Rd. Classical Helly's Theorem states that if a d-representable complex contains all the possible faces of dimension d then it is already a full simplex. Helly's Theorem has many extensions and we give a brief survey of some of them. The class of d-representable complexes is a subclass of d-collapsible complexes, and the latter is a subclass of d-Leray complexes. For d 1 we give an example of complexes that are 2d-Leray but not (3d 1)-collapsible. For d 2 we give an example of complexes that are d-Leray but not (2d 2)-representable. We show that for d 3 the complexes from the last example are also d-collapsible. We also give a simple proof of the Combinatorial Alexander Duality, which is a useful topological tool for combinatorics, e.g., for topological versions of Helly's Theorem.
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Fast Generator of Network Flows
Budiský, Jakub ; Dvořák, Milan (referee) ; Matoušek, Jiří (advisor)
Tato diplomová práce se věnuje analýze existujících řešení pro generování síťového provozu určeného k testování síťových komponent. Zaměřuje se na generátory na úrovni IP síťových toků a pokrývá návrh a implementaci generátoru, zvaného FLOR, schopného vytvářet syntetický síťový provoz rychlostí až několik desítek gigabitů za sekundu. K plánování toků využívá náhodného procesu. Vytvořená aplikace je otestována a porovnána s existujícími nástroji. V závěru jsou navrženy další vylepšení a optimalizace.
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Packet Filtration in 100 Gb Networks
Kučera, Jan ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
This master's thesis deals with the design and implementation of an algorithm for high-speed network packet filtering. The main goal was to provide hardware architecture, which would support large rule sets and could be used in 100 Gbps networks. The system has been designed with respect to the implementation on an FPGA card and time-space complexity trade-off. Properties of the system have been evaluated using various available rule sets. Due to the highly optimized and deep pipelined architecture it was possible to reach high working frequency (above 220 MHz) together with considerable memory reduction (on average about 72% for compared algorithms). It is also possible to efficiently store up to five thousands of filtering rules on an FPGA with only 8% of on-chip memory utilization. The architecture allows high-speed network packet filtering at wire-speed of 100 Gbps.
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Mapping of Match Tables from P4 Language to FPGA Technology
Kekely, Michal ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
This thesis deals with design and implementation of mapping of match action tables from P4 language to FPGA technology. Goal of the thesis was to describe key principles, which need to be understood in order to design such a mapping and function of algorithms needed, apply these principles by implementing them and analyze the speed and memory requirements of such an implementation. Outcome provides configurable hardware unit capable of classifying packets and connection between the unit and match action tables from P4 language. The implementation is based on DCFL algorithm and requires less memory compared to HiCuts and HyperCuts algorithms while being comparably fast at worst-case scenarios.
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Measurement of Backbone Routing Parameters
Celárek, Ondřej ; Kořenek, Jan (referee) ; Matoušek, Jiří (advisor)
This thesis deals with issue of routing between Autonomous Systems. For routing between autonomous systems is used Border Gateway Protocol (BGP). The routers in Autonomous Systems modify their routing tables based on BGP messages. Routing tables are used for forwarding information on Internet. Issue of this thesis is analysis of change routing tables for eventually optimizing of routing architecture. First part of thesis is focused on theory of routers, routing ang BGP. Second part of this thesis focuses on implementation and execution experiments with routing tables. In this part are also described reached results.
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Application Specific Processor for Stateful Network Traffic Processing
Kučera, Jan ; Matoušek, Jiří (referee) ; Kekely, Lukáš (advisor)
This bachelor's thesis deals with the design and implementation of an application-specific processor for high-speed network traffic processing. The main goal is to provide complex system for hardware acceleration of various network security and monitoring applications. The application-specific processor (hardware part of the system) is implemented on an FPGA card and has been designed with respect to be used in 100 Gbps networks. The design is based on the unique combination of high-speed hardware processing and flexible software control using a new concept called Software Defined Monitoring (SDM). The performance and throughput of the proposed system has been verified and measured.
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Packet Transmission at 100 Gb/s Ethernet
Hummel, Václav ; Dvořák, Milan (referee) ; Matoušek, Jiří (advisor)
The NetCOPE platform is used for rapid developement of hardware accelerated network applications on the family of COMBO cards. An essential part of this platform is output network module which helps designers to implement Data Link Layer of the OSI reference model, especially the MAC sublayer. This bachelor’s thesis focuses on design, implemen- tation and verification of such a module operating at speed 100 Gb/s. Furthemore, an appli- cation on the NetCOPE platform was created. It is designed for transmitting short samples of network traffic stored in QDR static memory. Transmission is controlled by precise ti- mestamps. The whole system was deployed on a COMBO card and verified by a network traffic analyzer.
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