|
|
Interactive Disassembler
Mrva, Milan ; Přikryl, Zdeněk (referee) ; Křoustek, Jakub (advisor)
This thesis describes procedures and tools of reverse engineering in terms of software development. There are introduces different techniques of protection against decomposition of executables. The work also mentions some programs used for decomposition analysis. Furthermore it contains information about architecture of processing units, with emphasis on microprocessors Intel and Motorola. Variety of executable formats is shown. Generic retargetable disassembler was implemented. There is a description of its structure and plugins. These plugins represents three algorithms used for disassembling a program. One of them applies a multi-process parsing engine, which is an own design by author of the thesis. At the end, these techniques are compared and further development is outlined.
|
|
|
Application for Detection of Plagiarism
Kačic, Matej ; Přikryl, Zdeněk (referee) ; Lukáš, Roman (advisor)
Main goal of this thesis is to create application, which can detect plagiarism in program code of projects without skeleton. It describes constructions of C/C++ language and their usage for detection of plagiarism. Projetcs are analysed by preprocesor, lexical analyse and phase of making structure of compare. After that they are compared one to each another by statistical test and Body test depends on Longest common subsequence.
|
|
| |
|
|
Compiler for Multicore Systems
Barteček, Jakub ; Přikryl, Zdeněk (referee) ; Masařík, Karel (advisor)
This bachelor´s thesis deals with parallel processing programs at the platform EdkDSP. The most important parts of this thesis are an analyzation of the target platform and a design of the translator. The design is aimed at translation of the OpenMP pragmas to a multithreaded code and a transformation of the specific types of cycles. The translator was implemented using the framework ROSE compiler and than tested.
|
|
|
Modelling of M68000 Model Processor
Adamec, Ondřej ; Přikryl, Zdeněk (referee) ; Masařík, Karel (advisor)
The goal of this bachelor's thesis is to create a model of Motorola 68000 processor using architecture description language CodAL and Codasip development environment. Architecture of the processor is presented and model structure is described. The result is a working model that has been tested to ensure its correctness.
|
|
|
Dynamic Reconfiguration of Hardware Accelerators
Brabec, Lukáš ; Přikryl, Zdeněk (referee) ; Masařík, Karel (advisor)
Thesis deals with usage of dynamic reconfiguration of FPGA in area of application specific instruction-set processors, considerng time-to-market, possibilities of acceleration and universality. Furthermore, it is designed an extension of application specific processor Codix with reconfigurable unit and it is described its implementation. Finally, the results are evaluated and opportunities for further development are identified.
|
|
|
Debugger for Generic Microprocessor Simulators
Wilczák, Milan ; Husár, Adam (referee) ; Přikryl, Zdeněk (advisor)
Application specific instruction set processors become part of every day life although it's not always visible at first sight. During their development it's needed to somehow describe their architecture, instruction set and behavior. To make their developement worth, it's necessary to be able to create applications for these processors and during application development errors are always made. Debuggers serve to discover and help fixing them. This paper summarises some basic information to debugger development and describes implementation for processors created using the Lissom project.
|
|
|
Implementation of Generic VLIW Processor in FPGA
Kuběna, Petr ; Přikryl, Zdeněk (referee) ; Husár, Adam (advisor)
VLIW processors are parallel computing devices that are used in embedded devices as well as in servers. My thesis contains description of this architecture. It is aimed at making and subsequently implementing design of custom general-purpose VLIW processor with wide range of configurable parameters. Operational implementation of such processor in VHDL which can be tested on FITkit platform is an integral part.
|
|
|
Implementation of General Disassembler
Přikryl, Zdeněk ; Masařík, Karel (referee) ; Lukáš, Roman (advisor)
This thesis presents the process of creating disassembler for new designed processors. We demand automatic generation of the disassembler. Instruction set for processor is modeled by specialized language ISAC, which offers resources for description of the instruction set. For example it describes format of instruction in the assembly language or format of instruction in the binary form or behavior of this instruction. Internal model is coupled finite automata, which describes relation of textual form of the instruction and binary form of the instruction in formal way. The code of disassembler is generated from the internal model. This disassembler accepts program in binary code at the input and generate equivalent program in assembly language at the output.
|
|
|
Analysis of the Possibility of Password Break through for RAR, ZIP and 7z Formats
Prustoměrský, Milan ; Přikryl, Zdeněk (referee) ; Hruška, Tomáš (advisor)
This Thesis deals with analysis of the possiblity of password breakthrough for common compression formats and password extraction from self-extraction archives used for malicious software. Structure of compression programs, ciphers and connection between cipher and archives is described. Common and specialized attacks on archives and ciphers are described. Structure of self-extracting archives and password location is used to create extractor of passwords in self-extracting archives.
|
guest ::
RSS feed.