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Longest Prefix Match Algorithms
Sedlář, František ; Matoušek, Jiří (referee) ; Tobola, Jiří (advisor)
This master's thesis explains basics of the longest prefix match (LPM) problem. It analyzes and describes chosen LPM algorithms considering their speed, memory requirements and an ability to implement them in hardware. On the basis of former findings it proposes a new algorithm Generic Hash Tree Bitmap. It is much faster than many other approaches, while its memory requirements are even lower. An implementation of the proposed algorithm has become a part of the Netbench library.
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Computer modelling of mixture formulas of composite materials
Matoušek, Jiří ; Frk, Martin (referee) ; Rozsívalová, Zdenka (advisor)
Submitted work engage in modelling of progressions of dielectric variables and aplication of mixture formulas for solution of composite materials in dependency on frequency. Theoretical part engage in theory of dielectric materials and composite materials and contains summary of basic mixture formulas. A part of work is programm which can be used in education. It allows modelling of permitivity, loss factor and loss number in dependency on frequency and Cole-Cole circle diagram in materials. In mixtures modelling of Maxwell´s, Bőttcher´s and Lichtenecker´s mixture formulas.
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Packet Filtration in 100 Gb Networks
Kučera, Jan ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
This master's thesis deals with the design and implementation of an algorithm for high-speed network packet filtering. The main goal was to provide hardware architecture, which would support large rule sets and could be used in 100 Gbps networks. The system has been designed with respect to the implementation on an FPGA card and time-space complexity trade-off. Properties of the system have been evaluated using various available rule sets. Due to the highly optimized and deep pipelined architecture it was possible to reach high working frequency (above 220 MHz) together with considerable memory reduction (on average about 72% for compared algorithms). It is also possible to efficiently store up to five thousands of filtering rules on an FPGA with only 8% of on-chip memory utilization. The architecture allows high-speed network packet filtering at wire-speed of 100 Gbps.
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Network Traffic Generator for Testing of Packet Classification Algorithms
Janeček, David ; Orsák, Michal (referee) ; Matoušek, Jiří (advisor)
Pokrok při zdokonalování klasifikačních algoritmů je zpomalován nedostatkem dat potřebných pro testování. Reálná data je obtížné získat z důvodu bezpečnosti a ochrany citlivých informací. Existují však generátory syntetických sad pravidel, jako například ClassBench-ng. K vyhodnocení správného fungování, propustnosti, spotřeby energie a dalších vlastností klasifikačních algoritmů je zapotřebí také vhodný síťový provoz. Tématem této práce je tvorba takového generátoru síťového provozu, který by umožnil testování těchto vlastností v kombinaci s IPv4, IPv6 a OpenFlow1.0 pravidly vygenerovanými ClassBench-ng. Práce se zabývá různými způsoby, jak toho dosáhnout, které vedly k vytvoření několika verzí generátoru. Vlastnosti jednotlivých verzí byly zkoumány řadou experimentů. Implementace byla provedena pomocí jazyku Python. Nejvýznamnějším výsledkem je generátor, který využívá principů několika zkoumaných přístupů k dosažení co nejlepších vlastností. Dalším přínosem je nástroj, který bylo nutné vytvořit pro analýzu užitých sad klasifikačních pravidel a vyhodnocení vlastností vygenerovaného síťového provozu.
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High-Speed Packet DMA Transfers from FPGA
Kubálek, Jan ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
Computer network devices that implement data-flow monitoring to allow network manage-ment require a high-speed receiving of a large amount of data for analysis. For a deviceto enable the monitoring of a network with high data traffic, its network interface cardneeds to be capable of transferring received data to a RAM at high speed. A new mo-dule for an FPGA chip on a network interface card, which can control these transfers, wasdesigned, implemented and tested in the course of this thesis. The created module sup-ports transfer of packets from the FPGA to the computer's memory via a PCI-Express busat the speed of 100 Gb/s and 200 Gb/s. Packets are transferred by DMA in system DPDK.
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Framework for Hardware Acceleration of 400Gb Networks
Hummel, Václav ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
The NetCOPE framework has proven itself as a viable framework for rapid development of hardware accelerated wire-speed network applications using Network Functions Virtualization (NFV). To meet the current and future requirements of such applications the NetCOPE platform has to catch up with upcoming 400 Gigabit Ethernet. Otherwise, it may become deprecated in following years. Catching up with 400 Gigabit Ethernet brings many challenges bringing necessity of completely different way of thinking. Multiple network packets have to be processed each clock cycle requiring a new concept of processing. Advanced memory management is used to ensure constant memory complexity with respect to the number of DMA channels without any impact on performance. Thanks to that, even more than 256 completely independent DMA channels are feasible with current technology. A lot of effort was made to create the framework as generic as possible allowing deployment of 400 Gigabit Ethernet and beyond. Emphasis is put on communication between the framework and host computer via PCI Express technology. Multiple Ethernet ports are also considered. The proposed system is prepared to be deployed on the family of COMBO cards, used as a reference platform.
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Framework for Dynamic Partial Reconfiguration of Virtex-5 FPGA
Raček, Jakub ; Viktorin, Jan (referee) ; Matoušek, Jiří (advisor)
The thesis is focused on design and implementiation of a framework for Dynamic Partial Reconfiguration for FPGA architecture Virtex-5. The aim of the framework is to simplify creating applications with hardware accelerators using Dynamic Partial Reconfiguration. Using this framework, a demonstration application was created for pattern-matching incoming network packets. The process of Dynamic Partial Reconfiguration is controlled by GNU/Linux type operating system, which runs on MicroBlaze processor. This also allows to run less demanding applications and the processing of packets using software.
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Implementation and Verification of Network Interface Blocks
Matoušek, Jiří ; Kaštil, Jan (referee) ; Tobola, Jiří (advisor)
Network interface blocks are basic part of the NetCOPE platform where they help to the network application designers to deal with problems of implementing the Data Link Layer of the OSI Reference Model, especially the MAC sublayer. This thesis is focused on the design and implementation of such network interface blocks operating at speed 10 Gb/s. Designed input interface block provides checking of several parts of the Ethernet frame and allows discarding of this frame based on checking results. Output interface block supports replacing frame's Source Address by a pre-set value and provides frame's CRC computation. Both network interface blocks also include a set of frames counters. Implemented network interface blocks were tested on the COMBO card. SystemVerilog verification testbench was also designed for both network interface blocks.
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Generation of Binary Prefix Tree According to Probabilistic Parameters
Ženčák, Tomáš ; Kučera, Jan (referee) ; Matoušek, Jiří (advisor)
The goal of this work is to create a prefix set generator which will be capable of generating a prefix set from parameters specified in the ClassBench toolset. This work describes a possible approach to generation, as well as the final algorithm for prefix set generation. The resulting generator is able to generate prefix sets whose average deviation from the target parameters is typically orders of magnitude lower than the deviation of sets generated by ClassBench.
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Network Traffic Simulation and Generation
Matoušek, Jiří ; Kořenek, Jan (referee) ; Korček, Pavol (advisor)
Development of computer networks able to operate at the speed of 10 Gb/s imposes new requirements on newly developed network devices and also on a process of their testing. Such devices are tested by replaying synthetic or previously captured network traffic on an input link of the tested device. We must be able to perform both tasks also at full wire speed. Current testing devices are either not able to operate at the speed of 10 Gb/s or they are too expensive. Therefore, the aim of this thesis is to design and implement a hardware accelerated application able to generate and replay network traffic at the speed of 10 Gb/s. The application is accelerated in the FPGA of the COMBOv2 card and it also utilizes the NetCOPE platform. Architecture of the application is modular, which allows easy implementation of different modes of operation. The application implements both capturing and replaying network traffic at full wire speed, but traffic can be limited to a specified value of bitrate at the output. The thesis is concluded by a comparison of the implemented application and the packet generator implemented on the NetFPGA platform. According to this comparison, the implemented application is better than the NetFPGA packet generator.
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