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A Design and Development of a Universal Power Supply for Laptops in Contemporary Motor Vehicles
Cagáň, Adam ; Levek, Vladimír (referee) ; Šťáva, Martin (advisor)
This thesis deals with design of DC power supply with adjustable output voltage in range of 15 to 30 V, working in buck-boost topology. Thesis explains selection of buck-boost controller integrated circuit and calculation of values of external components. Designed converter is supplied with overvoltage, overcurrent, and reverse voltage protection circuit. Final circuit is equipped with microcontroller, display, and rotary encoder, which make it easily operable. Further, there are compared parameters of the device achieved in simulation and in practice.
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A Digital Network-on-chip Architecture Model for Diagnostics
Valachovič, Marek ; Bohrn, Marek (referee) ; Šťáva, Martin (advisor)
Due to increasing integration on the chip, bus structure for on-chip comunication is less and less advantageous. For this reason, Network on Chip (NoC) was created as a solution to this problém. In this work, the basic blocks of the NoC architecture are described. The model of this architecture called Nonfire is described in detail, both function blocks, from which the router is created, and the network Interface Connecting this router with the Processing Element.
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High level synthesis in network applications described using P4 language
Panák, Petr ; Šťáva, Martin (referee) ; Fujcik, Lukáš (advisor)
High-level synthesis is a compelling method of designing a digital circuit. High abstraction and faster verification are advantages which aren't pressent in Register Transfer Level designing. That guarantees faster designing with lower development costs. This bachelor thesis deals with a digital design of actions, extern blocks and MI32 interface access. Each component design is described using C/C++ programming language and synthesised with Intel HLS compiler.
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A Hardware-acceleration Protocol Design for Demanding Computations over Multiple Cores
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with design of communication protocol for data transmission between control computer and computing cores implemented on FPGA chips. The purpose of the communication is speeding the performance demanding software algorithms of non-stream data processing by their hardware computation on accelerating system. The work defines a terminology used for protocol design and analyses current solutions of given issue. After that the work designs structure of the accelerating system and communication protocol. In the main part the work describes the implementation of the protocol in VHDL language and the simulation of implemented modules. At the end of the work the aplication of designed solution is presented along with possible extension of this work.
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Low-power Security System of the Electricity-free Cellars
Klimeš, Martin ; Levek, Vladimír (referee) ; Šťáva, Martin (advisor)
The work deals with the available options of security devices for basements, design and implementation of its own security system. An FPGA chip from Xilinx called XC3S50A was used as a device control. The device contains two motion sensors and a door passage sensor. There are two ways to report a breach. One way is the sound signaling by means of a siren and the other is the notification to the mobile phone by means of the GSM network.
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An Automated Hothouse for Young Orchid Plants
Chovančíková, Lucie ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
Constriction of automated greenhouse that shall secure ideal conditions for orchids in greenhouse (e.g. humidity, temperature, watering, air circulation etc.) is objective of this work. The first part deals with the analysis of current solutions whether commercial or professional. The second part of work describes greenhouse generally, there are technical parameters, purpose and function of single components. The third part of work occupies with proposal and construction of hardware, the fourth part occupies with description of VHDL specification. We can find out in two final part how greenhouse was construct and how it is possible to have control over greenhouse.
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An Encoder and Decoder of an Error-correction Code for Programmable Read-only Memories
Bareš, Jan ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
This work deals with theory of coding, analyses current groups of error correction codes and describes features and parametres of chosen representatives of these groups. By comparing these parametres along with given criteria it choses extended Hamming code as suitable code for securing read-only-memories (ROM). For this code it choses way of realization of synthetisable modules of coder and decoder and describes their design. The work describes design of synthetizable modules of coder and decoder in VHDL. Then it explains functionality of created application which is able to generate these synthetisable modules. For verification of generated modules it creates authentication environment. Part of this environment is also model of ROM allowing writing of any error value into the memory. In the end it automatically verifies generated modules of coder and decoder with various width of input information vector.
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Air Traffic Simulation with HackRF One
Mikan, Lukáš ; Dvořák, Vojtěch (referee) ; Šťáva, Martin (advisor)
Práce se zabývá problematikou simulace letového provozu v kontextu multilateračního přehledového systému. Technika multilaterace počítá polohu letounu coby průsečík hyperboloidů na základě rozdílů v čase příchodu zpráv z palubního transpondéru na různé pozice přijímacích antén. Při nahrazení každé antény SDR modulem lze vzdušný provoz nasimulovat pomocí umělých ADS-B zpráv, které jsou ve správných časech přivedeny do jednotlivých anténních vstupů. V této práci je použito SDR HackRF One, jehož hardware i firmware byl modifikován pro dosažení úzce synchronizovaného vysílání z potenciálně libovolného počtu propojených HackRF jednotek. Zde popsané úpravy zajišťují shodný kmitočet i fázi vzorkovacího hodinového signálu na všech HackRF, stejně jako současné spuštění přenosu. Ve druhé části práce je představeno algoritmické řešení umožňující sestavit fiktivní vzdušný scénář s libovolným počtem letů i přijímacích antén. Výstupem je sada datových streamů vhodná pro vyslání skrz synchronizovaná HackRF. Každý stream odpovídá specifické poloze antény v krajině a obsahuje přesně načasované zprávy standardu ADS-B, zakódovány pulzně-poziční modulací a převedeny na IQ vzorky. Celý systém umožňuje testovat správnou funkci reálného multilateračního sledovače, jako je například produkt MSS od firmy ERA, a.s.
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T1 Category Race Car Design
Šťáva, Martin ; Vančura, Jan (referee) ; Hejtmánek, Petr (advisor)
This diploma thesis deal with conceptual design of racing car of T1 category. Car consist of tubular frame, front and rear double wishbone suspension, braking system and conceptual design of the fairing. These are the basic of this thesis. For the completeness of the design, the location of the crew and the placement of the components inside the frame are also proposed. Adams Car 2016, Autodesk Inventor 2016, Ansys Workbench 18.1 were used for designing, testing, simulation and calculations. Designed T1 category race car meets International Automobile Federation (FIA) technical standards and safety regulatons.
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