National Repository of Grey Literature 880 records found  beginprevious859 - 868nextend  jump to record: Search took 0.00 seconds. 
Dynamic runtime partial reconfiguration in FPGA
Matoušek, Rudolf ; Daněk, Martin ; Pohl, Zdeněk ; Kadlec, Jiří
Runtime dynamic reconfiguration of FPGA devices has been an issue of the last decade. Although this feature permits more robust and more flexible designes and devices that posseses it are available on the market, it is not directly supported by the current design tools. This paper presents a simple design that uses true dymnamic reconfiguration for Atmel AT94K devices. The design has been implemented using a special feature of the currently available Figaro IDS5.2 tool in an innovative way.
Evolutionary techniques in physical design for FPGAs
Daněk, Martin ; Muzikář, Z.
This paper disscusses two studies of using evolutionary algorithms in physical design for FPGAs. The first study presents an adaptation of a genetic algorithm that optimises parametres of a linear delay model for Xilinx XC4000 FPGA and compares their performance to parameters optimised by hand. The second study showes implementation and performance of an adaptive technology mapping algorithm for XC4000 based on Wilsons XCS classifier system.
Prototyping of DSP algorithms on FPGA
Líčko, Miroslav ; Tichý, Milan ; Heřmánek, Antonín ; Matoušek, Rudolf ; Pohl, Zdeněk
Poster describes an algorithm development process for FPGA. The process is shown on the example of an implementation of the QR RLS algorithm.
Pasive coherent radiolocator - FPGA implementation of signal accelerator
Heřmánek, Antonín ; Kvasnička, M.
The paper presetns the implemantation of the HW architecture based on FPGA for CAF computation, which will by suitable for future real-time PCL systems.
Rekonfigurovatelná architektura pro zpracování obrazu s podporou rychlého modelování v Simulinku
Schier, Jan ; Kovář, Bohumil ; Zemčík, P. ; Herout, A. ; Beran, V.
A novel concept of an embedded image processing architecture is presented in the paper. This architecture is based on an interconnection of a programmable logical chip with a digital signal processor. Both these devices have characteristic that complement well each other for broad-class of data-intensive image-and video-processing tasks. For efficient utilization of such device, a multi-level configuration system is needed. The paper describes both the HW and SW architecture of the system.
Model přenosového systému záchranářského robotu Orpheus
Mazanec, Tomáš ; Heřmánek, Antonín ; Matoušek, Rudolf
The robotic platform Orpheus is a top-class reconnaissance system controlled by an innovative technology called telepresence.The transmissions system of the robot is very critical part, because it must provide short robot response time, while serving wide band video signal to the operator. Wi-Fi technology can handle both parameters, but it struggles with poor reliability in situations without line of sight between the robot and the operator's transmitter antenna. An article deals with a model in Matlab.

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