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High-Speed Packet DMA Transfers from FPGA
Kubálek, Jan ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
Computer network devices that implement data-flow monitoring to allow network manage-ment require a high-speed receiving of a large amount of data for analysis. For a deviceto enable the monitoring of a network with high data traffic, its network interface cardneeds to be capable of transferring received data to a RAM at high speed. A new mo-dule for an FPGA chip on a network interface card, which can control these transfers, wasdesigned, implemented and tested in the course of this thesis. The created module sup-ports transfer of packets from the FPGA to the computer's memory via a PCI-Express busat the speed of 100 Gb/s and 200 Gb/s. Packets are transferred by DMA in system DPDK.
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Testing Open vSwitch and DPDK
Šabart, Otto ; Grégr, Matěj (referee) ; Čejka, Rudolf (advisor)
The project is about the virtual switch called Open vSwitch and its architecture. It deals with an acceleration of the switch mainly by using Data Plane Development Kit (DPDK). Furthermore, it describes the architecture of the DPDK kit and analyses the individual functional units. Furthermore, it describes the architecture of the DPDK kit, analyses the individual functional units and describes the possibilities of its configuration. Another part of the project describes the methodology chosen for a performance testing of virtual switches. Subsequently, this methodology was used to make a design and environment implementation for fully automatic Open vSwitch s DPDK performance testing with the use of automatic systems such as Koji, Jenkins, Beaker a VSperf. Simultaneously, the tools for automatic comparison of produced results were implemented. The created environment was then used for the performance measurement of several basic Open vSwitch configurations with and without the use of DPDK. The implemented measurements are discussed and evaluated in the project. The final project's stage provides a great amount of the enlargement and improvement of the implemented tests.
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Framework for Hardware Acceleration of 400Gb Networks
Hummel, Václav ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
The NetCOPE framework has proven itself as a viable framework for rapid development of hardware accelerated wire-speed network applications using Network Functions Virtualization (NFV). To meet the current and future requirements of such applications the NetCOPE platform has to catch up with upcoming 400 Gigabit Ethernet. Otherwise, it may become deprecated in following years. Catching up with 400 Gigabit Ethernet brings many challenges bringing necessity of completely different way of thinking. Multiple network packets have to be processed each clock cycle requiring a new concept of processing. Advanced memory management is used to ensure constant memory complexity with respect to the number of DMA channels without any impact on performance. Thanks to that, even more than 256 completely independent DMA channels are feasible with current technology. A lot of effort was made to create the framework as generic as possible allowing deployment of 400 Gigabit Ethernet and beyond. Emphasis is put on communication between the framework and host computer via PCI Express technology. Multiple Ethernet ports are also considered. The proposed system is prepared to be deployed on the family of COMBO cards, used as a reference platform.
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Optimization of the Suricata IDS/IPS
Šišmiš, Lukáš ; Fukač, Tomáš (referee) ; Korček, Pavol (advisor)
V dnešnom svete zrýchľujúcej sa sieťovej prevádzky je potrebné držať krok v jej monitorovaní . Dostatočný prehľad o dianí v sieti dokáže zabrániť rozličným útokom na ciele nachádzajúce sa v nej . S tým nám pomáhajú systémy IDS, ktoré upozorňujú na udalosti nájdené v analyzovanej prevádzke . Pre túto prácu bol vybraný systém Suricata . Cieľom práce je vyladiť nastavenia systému Suricata s rozhraním AF_PACKET pre optimálnu výkonnosť a následne navrhnúť a implementovať optimalizáciu Suricaty . Výsledky z meraní AF_PACKET majú slúžiť ako základ pre porovnanie s navrhnutým vylepšením . Navrhovaná optimalizácia implementuje nové rozhranie založené na projekte Data Plane Development Kit ( DPDK ). DPDK je schopné akcelerovať príjem paketov a preto sa predpokladá , že zvýši výkon Suricaty . Zhodnotenie výsledkov a porovnanie rozhraní AF_PACKET a DPDK je možné nájsť na konci diplomovej práce .
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Network Traffic Analysis Using NXP Processor and FPGA
Orsák, Michal ; Vrána, Roman (referee) ; Kořenek, Jan (advisor)
The primary goal of this thesis is to exploit possibilites of aa entirely new hardware based on NXP LS2088 and FPGA. The secondary goal is to create firmware for this processor working out-of-box and perform optimisations of existing software for L7 analysis. This software was deeply bound to a previous hardware platform. The network processor NXP LS2088 contains many hardware accellerators and a virtual reconfigurable network. This thesis exploits all hardware parts of on this platform. Many tweaks and optimizations were performed based on this analysis to achieve maximum efficieny of software for L7 analysis. There were many intensive optimisations like rewriting for the DPDK library and new hardware or hardware synchronization of worker threads of this application. The main result of this thesis is working platform with efficient L7 analysis software which actively uses accelerators in FPGA and NXP network processor. SDK for new platform is also prepared.
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Implementation of 10 Gb Ethernet Interface for Arria 10 SoC
Novák, David ; Košař, Vlastimil (referee) ; Kořenek, Jan (advisor)
This thesis addresses design, implementation and testing of 10 Gb Ethernet interface for chip Arria 10 SoC (combination of FPGA and ARM Cortex-A9). Composition of the interface, its parts and communication between them is described with main focus being on MAC layer, which was designed and implemented in the course of this work. Secondary aspect of this thesis is increasing CPU performance demands for processing of packets and problems it brings. The performance of common CPUs is seriously lacking with network speeds over 10 Gb/s and alternative solutions has to be considered - namely acceleration of some tasks using FPGA and utilization of new ways of packet processing. Therefore, the description of DPDK (library for fast packet processing) as well as implementation of DPDK interface for newly created MAC module, are part of this thesis.
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Traffic Shaping in High Speed Networks in DPDK
Doležal, Pavel ; Fukač, Tomáš (referee) ; Vrána, Roman (advisor)
This bachelor thesis is focused on traffic shaping in high speed networks. It presents framework DPDK, which can be used for fast packet processing. General traffic shaping mechanisms are described as well as traffic shaping in Linux using program tc. It also introduces a design and implementation of traffic shaper using DPDK framework for networks with 10 Gbps bandwidth. The traffic shaper uses a complex mechanism of hierarchical token bucket. The system was tested using high speed traffic generator Spirent.
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Network Tasks Optimalization
Dražil, Jan ; Korček, Pavol (referee) ; Viktorin, Jan (advisor)
Nowdays, when we are running out of public IPv4 addresses, we rely on techniques that at least postpone their complete exhaustion. One of these techniques is a network address translation (NAT). Internet providers require the highest possible bandwidth from devices that perform this task. This thesis compares NAT DPDK, built on top of DPDK framework, with freely available alternatives. This work also extends NAT DPDK with Application-Level Gateway support.
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DPDK for COMBO Network Cards
Vido, Matej ; Dvořák, Milan (referee) ; Viktorin, Jan (advisor)
Software framework Data Plane Development Kit provides a standard API for fast packet processing in the user space. The DPDK covers multiple devices and architectures from different vendors. The CESNET association develops the family of COMBO network cards that are able to process Ethernet traffic up to 100 Gb/s through their SZE2 interface. This thesis describes the design and implementation of the DPDK user space driver for COMBO network cards. The driver is called szedata2 and has already become a part of the DPDK mainline in the version 2.2.0 (December 2015). The thesis describes also the measurements and the accomplished results. Packets have been received and transmitted at the wirespeed of the 100 Gb/s link.
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Accelerating an Application for DDoS Mitigation
Vojanec, Kamil ; Kekely, Lukáš (referee) ; Kučera, Jan (advisor)
This thesis focuses on optimizing and accelerating an application used for mitigating Denial of Service attacks. The goal is to analyze the existing implementation of DDoS Protector and to identify components which are suitable for optimization or hardware acceleration. Based on the analysis, improved algorithms and data structures utilizing the DPDK open-source framework are designed together with a proposal to offload certain computation elements into hardware using the RTE Flow library. The result of this thesis is a set of modules and an implementation of classification components intended to be used within the DDoS Protector application. The resulting components are then properly tested. Finally, the performance results of the original and new implementations are compared. The application shows as much as five-times improvement in terms of packet rate when using 256 classification rules.
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