National Repository of Grey Literature 383 records found  1 - 10nextend  jump to record: Search took 0.01 seconds. 
Web Based Simulator of Superscalar Processors
Majer, Michal ; Olšák, Ondřej (referee) ; Jaroš, Jiří (advisor)
A clear and interactive visualization of the superscalar processor is a valuable tool for studying its operation, particularly due to its complexity. The main contribution of this work is the extension of the existing RISC-V instruction set simulator with a new web-based user interface and improvements of the simulation quality. Nearly all modules of the simulator have been enhanced. Among other things, errors in the implementation have been resolved, statistics collection has been improved, and the instruction set has been expanded. The integration with the C language compiler is of great benefit. The simulator has been expanded to include HTTP and CLI interfaces. The React library has been utilized for implementing the web application. The result of the work is a functional and tested application, ready for practical use and with a positive impact on education.
Benchmark suite for graphics cards
Oškera, Josef ; Strnadel, Josef (referee) ; Jaroš, Jiří (advisor)
The goal of this work is to create a set of tasks for testing graphics cards so that someone else can try them out. This will be aided by a supporting application to run, debug and measure these tasks.
Playstation 1 Emulator with Higher Rendering Resolution
Stupka, Filip ; Šimek, Václav (referee) ; Jaroš, Jiří (advisor)
This thesis investigates the augmentation of visual fidelity in PlayStation 1 emulation by implementing advanced rendering techniques for higher resolution output. The study begins with a thorough analysis of the original hardware architecture, identifying components impacting graphical output. Focusing on developing a custom emulator, the research addresses challenges associated with upscaling graphics while maintaining compatibility with existing game software. The findings provide valuable insights for retro gaming enthusiasts and researchers, showcasing the successful implementation of a PlayStation 1 emulator with higher rendering resolution to preserve the legacy of classic games.
Optimisation of TSP-Based Tasks Using Collective Computational Intelligence
Franěk, Jaromír ; Jaroš, Jiří (referee) ; Bidlo, Michal (advisor)
The aim of this work is to compare collective computational intelligence algorithms for the optimization of large-scale instances of traveling salesman problem consisting of in several of thousands of cities. This work will be focused on optimization based on swarm behavior and optimization based on bee swarm behavior. I have compared individual algorithms from these two approaches with different parameters within a set of experiments. Based on these results, I proposed an improvement to the algorithms for solving the given problem. Then I proposed an improvement to the algorithms using diversity support methods, or local search for discrete versions of these algorithms. Finally, I compared results of proposed algorithms within a final set of experiments.
Improvement of the RISC-V CPU for the automotive industry
Gallo, Jiří ; Jaroš, Jiří (referee) ; Šimek, Václav (advisor)
Cílem této práce je úprava existujícího RISC-V procesoru pro použití v automobilovém průmyslu - konkrétně ovládání motorů. Tyto úpravy jsou založeny na ukázkovém kódu pro řízení motoru využívajícím aritmetiku s pevnou řádovou čárkou. Tento kód byl profilován a analyzován, na základě čehož byly vytvořeny nové instrukce. Vliv těchto instrukcí byl zanalyzován jak z pohledu zrychlení běhu, tak z pohledu dopadu na parametry procesoru.
Function animation of hip joint replacement
Sláčík, Tomáš ; Jaroš, Jan (referee) ; Nečas, David (advisor)
This bachelor thesis focuses on the function of the hip joint and its loading under variable kinematic and loading conditions. The main objective was to create animations of common daily movements.
Torsional stress fixture design using a universal testing machine
Kučík, Jiří ; Jaroš, Jan (referee) ; Vaverka, Ondřej (advisor)
This thesis aims to design a fixture for static torque testing for the Shimadzu AGX-V2 series universal testing machine. The fixture enables the mechanical conversion of linear motion to rotational motion and the securing of samples. The design includes the method of attaching the fixture to the machine, the geometry of the tested samples, and their fixation. The introductory part of the thesis provides a brief overview of possible motion conversion methods, the standardization of torque tests, and examples of several torque testing machines. The conceptual part focuses on designing variants of the fixture. Two variants are proposed: the first based on the principle of gears and the second on the principle of cams. These are compared using the finite element method. Based on the results, the fixture with the gear mechanism is selected, capable of torquing both solid and structured samples at an assumed maximum torque of 250 Nm. In the construction part, the final design of the mechanism is carried out and then verified using the finite element method and analytical strength calculations.
System for Control Automation of Home Brewery
Mimochodek, Vojtěch ; Jaroš, Jiří (referee) ; Šimek, Václav (advisor)
This thesis focuses on the control, automation, and monitoring of the beer brewing production process. The main goal is to develop a control system that enables the automation and monitoring of individual brewing phases. The theoretical part addresses the beer production processes, provides an overview of home brewing equipment, and offers a detailed description of the mini-brewery that is part of this thesis. The practical part includes the design and implementation of the proposed system. The Ąnal section is devoted to system testing and evaluation.
Design of Superscalar RISC-V Processor
Salvet, Dominik ; Šimek, Václav (referee) ; Jaroš, Jiří (advisor)
Tato práce se zabývá návrhem a implementací superskalární mikroarchitektury RISC-V procesoru zaměřené na prostředí s omezenými zdroji. Za tímto účelem mikroarchitektura definuje sedmistupňovou zřetězenou linku s dvojitým vydáváním instrukcí, které vykonává v pořadí. Je popsána v jazyce SystemVerilog a lze ji snadno simulovat na počítači. Pomocí připravených nástrojů pouští vytvořený model procesoru programy napsané v RISC-V jazyce symbolických adres zkompilované GCC. Na základě provedeného testování bez speciální asistence kompilátoru procesor provede v průměru 0,88 instrukcí za cyklus, čímž poskytuje o 22,6 % vyšší výkon než jeho skalární protějšek. Vzhledem k tomu, že se navržená mikroarchitektura také vyhýbá nadměrné specializaci, poskytuje dobrý základ, který lze dále rozšiřovat a optimalizovat na základě profilování očekávaných programů, což vede k optimálnímu výkonu a využití zdrojů.

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