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The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator
Bartosinski, Roman
The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform.
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Modelování sebeadaptujících se propojených prvků v Matlabu/Simulinku
Bartosinski, Roman ; Daněk, Martin ; Honzík, Petr ; Kadlec, Jiří
Recent developments in the digital technology make it cheaper and thus more accessible to an ordinary citizen. Currently almost any everyday device (car, fridge, cell phone) equipped with an electronic intelligence uses a programmable processing element. As the number of such networked devices will likely increase, and given the increased stress on low power consumption due to more strict environmental limitations, it is necessary to research novel techniques to program and use electronic devices more efficiently. This paper presents a framework for building and modeling new-generation self-adaptive systems. The first part of the paper describes an FPGA platform that implements a self-adaptive computing networked entity (SANE) that forms the basic element of the approach. The second part of the article describes a simulation and implementation framework in Matlab/Simulink for developing SANEs in FPGAs.
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Návrh řídicí aplikace s využitím Processor Expert blocksetu
Stružka, P. ; Waszniowski, L. ; Bartosinski, Roman ; Bysterský, T.
This paper describes design of a controller of the brushless DC motor using Processor Expert blockset in Mathworks Simulink. The controller algorithm is designed in Simulink and the Processor Expert blockset provides access to the microcontroller hardware through its Hardware Abstraction Layer. The behavior of the controller (including the peripherals represented by Processor Expert blocks) is verified by simulation. The Real-Time Workshop is used for the C source code generation from the controller model.
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Simulace hardwarových periferií MCU
Bartosinski, Roman ; Kadlec, Jiří
This paper describes one possible way, how MCU hardware peripherals (e.g. PWMs, Timers, ADCs, etc.) can be simulated in Matlab/Simulink environment and how code controlling these peripherals can be generated. The described implementation of the MCU hardware peripherals is based on using function call outputs as peripheral interrupts and external blocks called Methods as peripheral control functions. In the generated code by Real-Time Workshop, the Method block is represented by directly called corresponding function of the used periphery.
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