Original title:
The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator
Authors:
Bartosinski, Roman Document type: Papers Conference/Event: ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, Praha (CZ), 2011-05-22 / 2011-05-27
Year:
2011
Language:
eng Abstract:
The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform.
Keywords:
directional forgetting; hardware accelerator; LDU decomposition Project no.: CEZ:AV0Z10750506 (CEP), JU100230 Artemis, 7H10001 (CEP) Funding provider: GA MŠk, GA MŠk Host item entry: ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, ISBN 978-1-4577-0539-7