Original title: The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator
Authors: Bartosinski, Roman
Document type: Papers
Conference/Event: ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, Praha (CZ), 2011-05-22 / 2011-05-27
Year: 2011
Language: eng
Abstract: The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform.
Keywords: directional forgetting; hardware accelerator; LDU decomposition
Project no.: CEZ:AV0Z10750506 (CEP), JU100230 Artemis, 7H10001 (CEP)
Funding provider: GA MŠk, GA MŠk
Host item entry: ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, ISBN 978-1-4577-0539-7

Institution: Institute of Information Theory and Automation AS ČR (web)
Document availability information: Fulltext is available at external website.
External URL: http://library.utia.cas.cz/separaty/2011/ZS/bartosinski-0363078.pdf
Original record: http://hdl.handle.net/11104/0199178

Permalink: http://www.nusl.cz/ntk/nusl-55890


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Conference materials > Papers