Original title: Integrated iterative approach to FPGA placement
Authors: Daněk, Martin
Document type: Papers
Conference/Event: PAD 2003 Počítačové Architektury & Diagnostika, Zvíkovské Podhradí (CZ), 2003-09-24 / 2003-09-26
Year: 2003
Language: eng
Abstract: This paper describes a new iterative method based on an integrated timing-driven approach to the FPGA layout synthesis. The method uses a global routing to assess the quality of a placement. The placement and routing algorithms use an unified nonlinear cost function that takes into account both area and delay constraints imposed by a design, and eliminates effects of different signal net routing orders.
Keywords: FPGA placement; global routing; integrated approach
Project no.: CEZ:AV0Z1075907 (CEP), 0210413
Funding provider: CTU
Host item entry: Počítačové Architektury & Diagnostika PAD 2003

Institution: Institute of Information Theory and Automation AS ČR (web)
Document availability information: Fulltext is available at the institute of the Academy of Sciences.
Original record: http://hdl.handle.net/11104/0131282

Permalink: http://www.nusl.cz/ntk/nusl-35009


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Research > Institutes ASCR > Institute of Information Theory and Automation
Conference materials > Papers