Original title: Phase locked loops (PPL) design
Authors: Kroupa, Věnceslav František ; Štursa, Jarmil
Document type: Papers
Conference/Event: Aplikovaná elektronika'2000, Plzeň (CZ), 2000-09-06 / 2000-09-07
Year: 2000
Language: eng
Abstract: The sampled and higher order systems are discussed and means for stability checking, with the computer simulation of the Bode plots, are mentioned. It is shown that computer plotting of the PLL transfer function H(s) and 1-H(s), with the assistance of the open loop gain G(s), provides many information influence about noise of different noise sources; i.e., noise of the reference oscillator, of the voltage controlled oscillator, of the phase detector and of inevitable filters.
Keywords: Bode diagrams; frequency synthesizers; phase locked loops
Project no.: CEZ:AV0Z2067918 (CEP), GA102/00/0958 (CEP)
Funding provider: GA ČR
Host item entry: Aplikovaná elektronika'2000. Sborník referátů mezinárodní konference

Institution: Institute of Photonics and Electronics AS ČR (web)
Document availability information: Fulltext is available at the institute of the Academy of Sciences.
Original record: http://hdl.handle.net/11104/0113859

Permalink: http://www.nusl.cz/ntk/nusl-32446


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Research > Institutes ASCR > Institute of Photonics and Electronics
Conference materials > Papers