Original title: Clock Domain Crossing Interfaces
Authors: Cabal, J.
Document type: Papers
Language: cze
Publisher: Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract: This work presents an easy-to-use library of clock domain crossing modules and a methodology for it's use. These crossings are inevitable in moderately complex firmware designs. Incorrectly implemented clock domain crossing modules can lead to data corruption or data loss. For correct functionality of these crossings it is necessary to apply correct constraints. Automatic application of contraints is a part of the created library. Its easy use is also supported by the methodology for selection of correct clock domain crossing module in the form of a decision tree.
Keywords: CDC; FPGA; metastability; Vivado
Host item entry: Proceedings of the 21st Conference STUDENT EEICT 2015, ISBN 978-80-214-5148-3

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/42923

Permalink: http://www.nusl.cz/ntk/nusl-220453


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Universities and colleges > Public universities > Brno University of Technology
Conference materials > Papers