Original title: Vysokorychlostní akviziční systém
Translated title: High speed acquisition system
Authors: Svoboda, Tomáš ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
Document type: Master’s theses
Year: 2018
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií
Abstract: [cze] [eng]

Keywords: AD converter; ADC; FPGA; JESD204B; lwIP; Microblaze; Xilinx; AD převodník; ADC; FPGA; JESD204B; lwIP; Microblaze; Xilinx

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/80953

Permalink: http://www.nusl.cz/ntk/nusl-377119


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2018-06-19, last modified 2019-03-28


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